# US 8,787,104 B2 · Semiconductor memory device

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- Number: US 8,787,104 B2
- Document ID: US8787104B2
- Status: Granted
- Kind: B2
- Application number: 13/243,245
- Filed: 2011-09-23
- Published: 2012-07-05
- Granted: 2014-07-22
- Earliest claimed: 2010-12-29
- Assignees: SK hynix Inc.
- Applicants: Keun Kook Kim
- Inventors: Keun Kook Kim
- Web page: https://patentgrep.com/patent/US8787104B2

## CPC

- G11C 11/40626: {Temperature related aspects of refresh operations}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor memory device includes a temperature sensor configured to generate a low-temperature signal which is enabled at below first set temperature and a high-temperature signal which is enabled at above second set temperature; a start signal generator configured to receive a refresh command and generate a start signal according to the low-temperature signal; and an address counter configured to count refresh addresses in response to the start signal.

## Claims

### Claim 1

A semiconductor memory device comprising:
a temperature sensor configured to generate a low-temperature signal which is enabled at below first set temperature and a high-temperature signal which is enabled at above second set temperature;
a start signal generator configured to receive a refresh command and generate a start signal according to the low-temperature signal; and
an address counter configured to count refresh addresses in response to the start signal,
wherein the address counter outputs a larger number of refresh addresses when the low-temperature signal is enabled than when the low-temperature and the high-temperature signal are disabled.

### Claim 2 (depends on 1)

The semiconductor memory device of claim 1, wherein the first set temperature is set to be lower than the second set temperature.

### Claim 3 (depends on 1)

The semiconductor memory device of claim 1, wherein, if the low-temperature signal is enabled, the start signal generator generates the start signal after at least two refresh commands are inputted.

### Claim 4 (depends on 1)

The semiconductor memory device of claim 1, wherein the address counter counts a smaller number of refresh addresses when the high-temperature signal is enabled than when the low-temperature signal and the high-temperature signal are disabled.

### Claim 5 (depends on 1)

The semiconductor memory device of claim 1, further comprising a row decoder configured to decode the refresh addresses and generate row addresses for refreshing memory cells included in a memory cell array.