# US 8,787,103 B2 · Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device

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- Number: US 8,787,103 B2
- Document ID: US8787103B2
- Status: Granted
- Kind: B2
- Application number: 13/187,665
- Filed: 2011-07-21
- Published: 2011-11-10
- Granted: 2014-07-22
- Earliest claimed: 2007-09-07
- Assignees: Micron Technology, Inc.
- Applicants: Vishal Sarin; Jung-Sheng Hoei; Frankie F. Roohparvar
- Inventors: Vishal Sarin; Jung-Sheng Hoei; Frankie F. Roohparvar
- Web page: https://patentgrep.com/patent/US8787103B2

## CPC

- G11C 16/06: Auxiliary circuits, e.g. for writing into memory
- G11C 11/5621: {using charge storage in a floating gate}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 27/005: {with non-volatile charge storage, e.g. on floating gate or MNOS}
- G11C 7/16: Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters
- G11C 2211/5634: Reference cells
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array.

## Claims

### Claim 1

A memory device comprising:
a plurality of memory cells;
a plurality of reference memory cells that are a subset of the plurality of memory cells, wherein a first group of at least two reference memory cells of the plurality of reference memory cells are used to define an upper limit, wherein a second group of at least two reference memory cells of the plurality of reference memory cells are used to define a lower limit, wherein the second group uses different reference memory cells than the first group; and
an analog-to-digital conversion circuit coupled to the plurality of memory cells, wherein the analog-to-digital conversion circuit receives the upper limit and lower limit to define the conversion window.

### Claim 2 (depends on 1)

The memory device of claim 1 wherein the memory cells are configured to store a voltage that represents a digital bit pattern.

### Claim 3 (depends on 1)

The memory device of claim 1 wherein each reference memory cell is configured to store a different reference voltage.

### Claim 4 (depends on 1)

The memory device of claim 1 wherein the plurality of reference memory cells are configured to track a temperature of the plurality of memory cells;

### Claim 5 (depends on 1)

The memory device of claim 1 and further comprising a buffer circuit to buffer the upper limit and the lower limit.

### Claim 6 (depends on 1)

The memory device of claim 1 wherein each of the plurality of memory cells is configured to be a multi-level cell.

### Claim 7

A storage system comprising:
a plurality of memory cells, the plurality of memory cells further comprising:
a first pair of reference memory cells comprising a first reference memory cell for storing a first reference voltage and a second reference memory cell for storing a second reference voltage, wherein the first pair of reference memory cells are used to define an upper limit; and
a second pair of reference memory cells comprising a third reference memory cell for storing a third reference voltage and a fourth reference memory cell for storing a fourth reference voltage, wherein the second pair of reference memory cells are used to define a lower limit;
a buffer circuit to buffer the upper limit and lower limit;
an analog-to-digital converter coupled to the memory array and the pair of reference memory cells, the analog-to-digital converter using the upper limit for a conversion window and the buffered lower limit for the conversion window such that the conversion window defines limits of a conversion process on each analog voltage wherein the conversion window is configured to move with a temperature of the plurality of memory cells.

### Claim 8 (depends on 7)

The system of claim 7 and further including a controller coupled to the analog-to-digital converter that is configured to control the conversion process.

### Claim 9 (depends on 7)

The system of claim 7 and further including a digital-to-analog converter coupled to the memory array for providing analog voltages to the plurality of memory cells responsive to digital data.

### Claim 10 (depends on 9)

The system of claim 9 and further including a controller coupled to the plurality of memory cells, the controller comprising the analog-to-digital converter and the digital-to-analog converter.

### Claim 11 (depends on 7)

The system of claim 7 wherein the buffering circuit is a sample and hold circuit.

### Claim 12 (depends on 11)

The system of claim 11 wherein the sample and hold circuit is configured to provide amplification.

### Claim 13 (depends on 11)

The system of claim 11 wherein the sample and hold circuit comprises analog storage devices.

### Claim 14

A method for adjusting a conversion window, the method comprising:
programming, at a predetermined temperature, a first reference voltage to a first reference cell, in a plurality of memory cells, that is configured to track a temperature of the plurality of memory cells;
programming, at the predetermined temperature, a second reference voltage to a second reference cell, in the plurality of memory cells, that is configured to track the temperature of the plurality of memory cells, wherein the second reference voltage is different than the first reference voltage;
programming a third reference voltage to a third reference memory cell, in the memory array, that is configured to track a temperature of the plurality of memory cells;
programming a fourth reference voltage to a fourth reference memory cell, in the plurality of memory cells, that is configured to track a temperature of the plurality of memory cells;
receiving a plurality of reference voltages;
defining an upper limit based upon a first group of reference voltages from at least two of the first, second, third, and fourth reference memory cells;
defining a lower limit based upon a second group of reference voltages from at least two of the first, second, third, and fourth reference memory cells, wherein the second group is different than the first group; and
defining the conversion window in response to the upper limit and the lower limit.

### Claim 15 (depends on 14)

The method of claim 14 wherein the predetermined temperature is substantially room temperature.

### Claim 16 (depends on 14)

The method of claim 14 wherein the plurality of reference voltages are based on memory cell characteristics of memory cell process technology.

### Claim 17

A memory system comprising:
a plurality of non-volatile memory cells;
a first reference memory cell for storing a first reference voltage, the first reference memory cell further configured to track a temperature of the memory array;
a second reference memory cell for storing a second reference voltage different than the first reference voltage, the second reference memory cell further configured to track a temperature of the memory array;
a third reference memory cell for storing a third reference voltage, the third reference memory cell further configured to track a temperature of the memory array;
a fourth reference memory cell for storing a fourth reference voltage, the fourth reference memory cell further configured to track a temperature of the memory array;
wherein a first group of at least two of the first, second, third, and fourth reference memory cells are used to define an upper limit, wherein a second group of at least two of the first, second, third, and fourth reference memory cells are used to define a lower limit, wherein the second group uses different reference memory cells than the first group;
a buffer circuit to buffer the upper limit and lower limit; and
an analog-to-digital converter circuit, coupled to the plurality of memory cells and configured to convert an analog voltage from at least one of the plurality of memory cells to a digital bit pattern representative of the analog voltage in response to an analog-to-digital conversion window formed by the buffered upper limit and the buffered lower limit, such that an analog-to-digital conversion window moves with the temperature of the memory array.

### Claim 18 (depends on 17)

The system of claim 17 wherein the analog-to-digital conversion circuit is separate from a memory device comprising the plurality of memory cells.

### Claim 19 (depends on 18)

The system of claim 18 wherein the analog-to-digital converter circuit is part of a controller circuit coupled to, but not part of, the memory device.

### Claim 20 (depends on 19)

The system of claim 19 wherein the plurality of memory cells are floating gate memory cells.