# US 8,787,101 B2 · Stacked device remapping and repair > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,101 B2 - Document ID: US8787101B2 - Status: Granted - Kind: B2 - Application number: 13/959,395 - Filed: 2013-08-05 - Published: 2013-12-12 - Granted: 2014-07-22 - Earliest claimed: 2008-10-07 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Brent Keeth; Chris G. Martin; Troy A. Manning; Joe M. Jeddeloh; Timothy B. Cowles; Jim Rehmeyer; Paul A. LaBerge - Web page: https://patentgrep.com/patent/US8787101B2 ## CPC - G06F 12/08: in hierarchically structured memory systems, e.g. virtual memory systems - G06F 12/10: Address translation - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 29/808: {using a flexible replacement scheme} - G11C 29/883: {using a single defective memory device with reduced capacity, e.g. half capacity} - G11C 29/04: Detection or location of defective memory elements {, e.g. cell constructio details, timing of test signals} - G11C 29/18: Address generation devices; Devices for accessing memories, e.g. details of addressing circuits - G11C 29/76: {using address translation or modifications} - G11C 29/78: {using programmable devices} - G11C 29/812: {using a reduced amount of fuses} - H10W 72/07254: {changes in dispositions} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/247: {Dispositions of multiple bumps} - H10W 72/90: Bond pads, in general - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Various embodiments include apparatus, systems, and methods having multiple dice arranged in a stack in which a defective cell may be replaced by a spare cell on the same die or a different die. Other embodiments are described. ## Claims ### Claim 1 An apparatus comprising: a plurality of dice arranged in a stack, the plurality of dice including cells; and an additional die configured to organize a memory address space into an addressable memory address space portion and a non-addressable memory address space portion, the addressable memory address space portion associated with non-defective cells among the cells, the non-addressable memory address space portion associated defective cells among the cells, wherein the addressable memory address space portion is a contiguous memory address space portion. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the non-addressable memory address space portion is a contiguous memory address space portion. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the additional die is configured to remap an address of a defective cell among the cells to a non-defective cell among the cells. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the defective cell and the non-defective cell are located at the same die among the dice. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the defective cell is located at a first die among the dice and the non-defective cell is located at a second die among the dice. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the additional die includes a spare cell to replace one of the defective cells. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the spare cell and the defective cell are different cell types. ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the apparatus comprises a memory device, the memory device configured to disable at least one address in the non-addressable memory address space portion. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the apparatus comprises a memory device, the memory device configured to provide another device the addressable memory address space portion during an initialization period. ### Claim 10 An apparatus comprising: a plurality of dice arranged in a stack, the plurality of dice including cells; and an additional die configured to organize a memory address space into an addressable memory address space portion and a non-addressable memory address space portion, the addressable memory address space portion associated with non-defective cells among the cells, the non-addressable memory address space portion associated defective cells among the cells, wherein the additional die is configured to mask at least one address of at least one defective cell among the cells from an external device. ### Claim 11 (depends on 10) The apparatus of claim 10, wherein the additional die includes additional cells, and the addressable memory address space portion is further associated with non-defective cells among the additional cells. ### Claim 12 (depends on 10) The apparatus of claim 10, wherein the additional die is configured to remap at least one address of at least one defective cell among the cells and the additional cells to at least one non-defective cell among the cells and the additional cells. ### Claim 13 (depends on 10) The apparatus of claim 10, wherein at least one of the dice and the additional die includes at least one spare cell to replace a defective cell in one of the dice and the additional die. ### Claim 14 (depends on 10) The apparatus of claim 10, wherein the addressable memory address space portion is a contiguous memory address space portion. ### Claim 15 (depends on 10) The apparatus of claim 10, wherein the addressable memory address space portion is a noncontiguous memory address space portion. ### Claim 16 (depends on 10) The apparatus of claim 10, wherein the non-addressable memory address space portion is a contiguous memory address space portion. ### Claim 17 A method comprising: providing a plurality of dice arranged in a stack, the plurality of dice including a plurality cells; providing an additional die; and organizing at the additional die a memory address space into an addressable memory address space portion and a non-addressable memory address space portion, the addressable memory address space portion associated with non-defective cells of the plurality of cells, the non-addressable memory address space portion associated defective cells of the plurality of cells, wherein the addressable memory address space portion is a contiguous addressable space portion. ### Claim 18 (depends on 17) The method of claim 17, wherein addresses in the addressable memory address space portion have higher values than addresses in the non-addressable memory address space portion. ### Claim 19 (depends on 17) The method of claim 17, wherein addresses in the addressable memory address space portion have lower values than addresses in the non-addressable memory address space portion. ### Claim 20 (depends on 17) The method of claim 17, further comprising: making addresses in the non-addressable memory address space portion unavailable.