# US 8,787,100 B2 · Non-volatile memory device generating a reset pulse based on a set pulse, and method of operating the same

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- Number: US 8,787,100 B2
- Document ID: US8787100B2
- Status: Granted
- Kind: B2
- Application number: 13/710,504
- Filed: 2012-12-11
- Published: 2013-10-10
- Granted: 2014-07-22
- Earliest claimed: 2012-04-10
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Yong Jin Kwon; Kwang Jin Lee; Hye-Jin Kim
- Inventors: Yong Jin Kwon; Kwang Jin Lee; Hye-Jin Kim
- Web page: https://patentgrep.com/patent/US8787100B2

## CPC

- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0061: {Timing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 29/021: {in voltage or current generators}
- G11C 29/023: {in clock generator or timing circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 13/00: Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C 2013/0088: {Write with the simultaneous writing of a plurality of cells}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A non-volatile memory device includes a set pulse generator configured to generate a set pulse, a reset pulse generator configured to generate a reset pulse based on the set pulse, and a write driver block configured to write second data to a second non-volatile memory cell using the reset pulse, while writing first data to a first non-volatile memory cell using the set pulse.

## Claims

### Claim 1

A method of operating a non-volatile memory device comprising:
generating a set pulse for writing first data to a first memory cell; and
generating a reset pulse based on the set pulse after programmed delay for writing second data to a second memory cell.

### Claim 2 (depends on 1)

The method of claim 1, wherein the programmed delay is determined based on information set in a programmable memory.

### Claim 3 (depends on 2)

The method of claim 2, wherein the programmed delay is determined based on whether each fuse of the programmable memory is cut.

### Claim 4 (depends on 1)

The method of claim 1, wherein the reset pulse is generated when the set pulse is activated.

### Claim 5 (depends on 1)

The method of claim 1, wherein the reset pulse is generated when the set pulse is deactivated.

### Claim 6 (depends on 1)

The method of claim 1, wherein the reset pulse is generated such that the reset pulse is deactivated when the set pulse is deactivated.

### Claim 7

A method of operating a non-volatile memory device comprising:
generating a set pulse; and
generating a reset pulse based on the set pulse after programmed delay,
wherein the reset pulse is generated such that a duration of the reset pulse exists within a duration of the set pulse.

### Claim 8 (depends on 1)

The method of claim 1, wherein the set pulse comprises a plurality of pulses having overlapping durations, and wherein the reset pulse is generated based on one pulse of the plurality of pulses.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
selecting and outputting the one pulse of the plurality of pulses in response to selection signals corresponding to the programmed delay.

### Claim 10 (depends on 7)

The method of claim 7, further comprising:
substantially simultaneously programming second data to a second non-volatile memory cell using the reset pulse and first data to a first non-volatile memory cell using the set pulse.

### Claim 11 (depends on 1)

The method of claim 1, further comprising:
writing the second data corresponding to the reset pulse to the second memory cell using a second switching circuit that operates in response to a switching signal, while writing the first data corresponding to the set pulse to the first memory cell using a first switching circuit that operates in response to the switching signal,
wherein the switching signal is deactivated in response to deactivation of one of the set pulse and the reset pulse.

### Claim 12

A method of operating a non-volatile memory device, the method comprising:
generating a reset pulse based on a set pulse;
providing a reset signal generated according to the reset pulse to a second non-volatile memory cell, while providing a set signal generated according to the set pulse to a first non-volatile memory cell; and
simultaneously blocking the set signal from being supplied to the first non-volatile memory cell and the reset signal from being supplied to the second non-volatile memory cell, in response to deactivation of one of the set pulse and the reset pulse.