# US 8,787,096 B1 · N-well switching circuit

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,787,096 B1
- Document ID: US8787096B1
- Status: Granted
- Kind: B1
- Application number: 13/742,964
- Filed: 2013-01-16
- Published: 2014-07-17
- Granted: 2014-07-22
- Earliest claimed: 2013-01-16
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Esin Terzioglu; Gregory Ameriada Uvieghara; Sei Seung Yoon; Balachander Ganesan; Anil Chowdary Kota
- Web page: https://patentgrep.com/patent/US8787096B1

## CPC

- H03K 17/223: {in field-effect transistor switches}
- G11C 7/00: Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413)
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 17/18: Auxiliary circuits, e.g. for writing into memory
- H03K 17/08104: {in field-effect transistor switches (H03K17/0812, H03K17/0814 take precedence)}
- H03K 17/6872: {using complementary field-effect transistors}
- H03K 19/00315: {in field-effect transistor circuits}
- G11C 13/0069: {Writing or programming circuits or methods}
- H03K 2217/0018: Special modifications or use of the back gate voltage of a FET
- H03K 2217/0063: High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
- H03K 2217/0072: Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A dual-mode PMOS transistor is disclosed that has a first mode of operation in which a switched n-well for the dual-mode PMOS transistor is biased to a high voltage. The dual-mode PMOS transistor has a second mode of operation in which the switched n-well is biased to a low voltage that is lower than the high voltage. The dual-mode PMOS transistor has a size and gate-oxide thickness each having a magnitude that cannot accommodate a permanent tie to the high voltage. An n-well voltage switching circuit biases the switched n-well to prevent voltage damage to the dual-mode PMOS transistor despite its relatively small size and thin gate-oxide thickness.

## Claims

### Claim 1

A voltage switching circuit, comprising:
an NMOS transistor having a gate controlled responsive to a control signal, a drain coupled to a low-voltage supply configured to provide a low voltage, and a source coupled to a switched n-well for a dual-mode PMOS transistor; and
a first PMOS transistor having a gate controlled responsive to the control signal, a source coupled to a high-voltage supply configured to provide a high voltage that is greater than the low voltage, and a drain coupled to the switched n-well.

### Claim 2 (depends on 1)

The voltage switching circuit of claim 1, further comprising an inverter configured to invert the control signal into an inverted control signal, and wherein the gate for the NMOS transistor and the gate for the first PMOS transistor are configured to be driven by the inverted control signal.

### Claim 3 (depends on 2)

The voltage switching circuit of claim 2, wherein the NMOS transistor is a native NMOS transistor.

### Claim 4 (depends on 2)

The voltage switching circuit of claim 2, wherein the first PMOS transistor includes an un-switched n-well permanently coupled to the high-voltage supply.

### Claim 5 (depends on 4)

The voltage switching circuit of claim 4, wherein the first PMOS transistor has a first size and wherein the dual-mode PMOS transistor has a second size smaller than the first size.

### Claim 6 (depends on 5)

The voltage switching circuit of claim 5, wherein the first PMOS transistor has a first gate-oxide thickness and wherein the dual-mode PMOS transistor has a second gate-oxide thickness that is less than the first gate-oxide thickness.

### Claim 7 (depends on 6)

The voltage switching circuit of claim 6, wherein the first size and the first gate-oxide thickness each have a magnitude sufficient to protect the first PMOS transistor from its un-switched n-well being permanently coupled to the high-voltage supply.

### Claim 8 (depends on 6)

The voltage switching circuit of claim 6, wherein the second size and the second gate-oxide thickness each have a magnitude that is not sufficient to protect the dual-mode PMOS transistor from a permanent tie of the high-voltage supply to the switched n-well.

### Claim 9

A memory, comprising:
an n-well voltage switching circuit configured to selectively drive an output node to a low voltage and to a high voltage that is greater than the low voltage, the n-well voltage switching circuit including a thick gate-oxide PMOS transistor;
a word line driver PMOS transistor having a source and a switched n-well tied to the output node, wherein the word line driver PMOS transistor has a thin gate-oxide thickness that is less than a gate-oxide thickness for the thick gate-oxide PMOS transistor.

### Claim 10 (depends on 9)

The memory of claim 9, wherein the memory is an electrical programmable memory further comprising an e-fuse having a terminal coupled to a drain of a thin gate-oxide programming NMOS transistor, the thin gate-oxide programming NMOS transistor having its gate coupled to a word line, the word line being coupled to a drain for the word line driver PMOS transistor.

### Claim 11 (depends on 10)

The memory of claim 10, further comprising a bit line coupled to an opposing terminal of the e-fuse.

### Claim 12 (depends on 11)

The memory of claim 11, further comprising a high power switch for biasing the bit line to the high voltage during a programming mode for the e-fuse.

### Claim 13 (depends on 12)

The memory of claim 12, wherein the high power switch includes a global power switch and a local power switch in series between the bit line and a high voltage supply configured to supply the high voltage.

### Claim 14 (depends on 13)

The memory of claim 13, wherein the local power switch comprises a PMOS transistor having a switched n-well coupled to the output node of the n-well voltage switching circuit.

### Claim 15 (depends on 11)

The memory of claim 11, wherein the memory is incorporated into at least one of a cellphone, a laptop, a tablet, a music player, a communication device, a computer, and a video player.

### Claim 16

A method, comprising:
responsive to receiving a control signal in a first state at an n-well voltage switching circuit, biasing a switched n-well of a dual-mode PMOS transistor with a first voltage, wherein the n-well voltage switching circuit comprises transistors of a first size and a first gate-oxide thickness, and wherein the dual-mode PMOS transistor has a second size that is less than the first size and a second gate-oxide thickness that is less than the first gate-oxide thickness, and
responsive to receiving the control signal in a second state at the n-well voltage switching circuit, biasing the switched n-well with a second voltage that is less than the first voltage.

### Claim 17 (depends on 16)

The method of claim 16, further comprising controlling a duration for the receipt of the control signal in the first state such that the dual-mode PMOS transistor is not damaged by the bias of its switched n-well with the first voltage.

### Claim 18 (depends on 16)

The method of claim 16, wherein the dual-mode PMOS transistor is a word line driver transistor for an electrically programmable memory, and wherein biasing the switched n-well with the first voltage comprises programming an e-fuse through the word line driver transistor.

### Claim 19 (depends on 18)

The method of claim 18, wherein biasing the switched n-well with the second voltage comprises reading a state of the e-fuse.

### Claim 20 (depends on 18)

The method of claim 18, further comprising biasing a bit line coupled to the e-fuse to the high voltage during the programming of the e-fuse, wherein biasing the bit line comprises biasing the bit line through a local power switch PMOS transistor having a switched n-well biased by the n-well voltage switching circuit to the second voltage.