# US 8,787,095 B2 · Systems, and devices, and methods for programming a resistive memory cell > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,095 B2 - Document ID: US8787095B2 - Status: Granted - Kind: B2 - Application number: 13/407,007 - Filed: 2012-02-28 - Published: 2013-08-29 - Granted: 2014-07-22 - Earliest claimed: 2012-02-28 - Assignees: Micron Technology, Inc. - Applicants: Xiaonan Chen - Inventors: Xiaonan Chen - Web page: https://patentgrep.com/patent/US8787095B2 ## CPC - G11C 13/0069: {Writing or programming circuits or methods} - G11C 11/5678: {using amorphous/crystalline phase transition storage elements} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 2013/0092: {Write characterized by the shape, e.g. form, length, amplitude of the write pulse} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Embodiments disclosed herein may relate to programming a memory cell with a programming pulse that includes a quenching period. The quenching period includes an initial portion and a subsequent portion, with the subsequent portion different than the initial portion. During the initial portion, the amplitude of the programming pulse may be reduced to a first target amplitude level, and during the subsequent portion, the amplitude of the programming pulse may be further reduced to a second target amplitude level. ## Claims ### Claim 1 A method, comprising: programming a memory cell with a sequence of electrical pulses, wherein the sequence comprises a set electrical pulse, and wherein the sequence also comprises an electrical pulse, wherein the electrical pulse comprises a quenching period including an initial portion and a subsequent portion, wherein the subsequent portion is different than the initial portion. ### Claim 2 (depends on 1) The method of claim 1, wherein the programming the memory cell comprises reducing an amplitude of the electrical pulse from an initial amplitude level to a target amplitude level during the initial portion of the quenching period. ### Claim 3 (depends on 2) The method of claim 2, wherein the amplitude level comprises at least one of the following: a current amplitude level or a voltage amplitude level. ### Claim 4 (depends on 2) The method of claim 2, wherein the programming the memory cell comprises reducing the amplitude from the target amplitude level, comprising a first target amplitude level, to a second target level during the subsequent portion of the quenching period. ### Claim 5 (depends on 1) The method of claim 1, wherein the programming the memory cell with the electrical pulse comprises the subsequent portion of the quenching period comprising a target falling edge corresponding to a target programmed state. ### Claim 6 (depends on 5) The method of claim 5, wherein the target falling edge, comprising a target duration of time, comprises one of a plurality of falling edges, the plurality of falling edges corresponding to a plurality of respective programmed states. ### Claim 7 (depends on 1) The method of claim 1, further comprising programming the memory cell with an additional electrical pulse to a particular target programmed state. ### Claim 8 (depends on 7) The method of claim 7, further comprising performing a verify operation on the memory cell. ### Claim 9 (depends on 7) The method of claim 7, wherein the programming the memory cell with the additional electrical pulse comprises programming the memory cell with a staircase up sequence of electrical pulses. ### Claim 10 (depends on 1) The method of claim 1, wherein a duration of time of the subsequent portion exceeds a duration of time of the initial portion. ### Claim 11 A memory device, comprising: a memory array comprising a plurality of memory cells; and a control unit to program a memory cell of the plurality of memory cells using an electrical pulse, wherein the electrical pulse comprises a quenching period including an initial portion and a subsequent portion, the subsequent portion being different than the initial portion and having a durations of time equal to or greater than approximately 50 ns. ### Claim 12 (depends on 11) The memory device of claim 11, wherein control unit is further to select the subsequent portion from among a plurality of subsequent portions corresponding to a plurality of respective programmed states. ### Claim 13 (depends on 11) The memory device of claim 11, wherein the initial portion comprises a duration of time of approximately 5 ns. ### Claim 14 (depends on 11) The memory device of claim 11, wherein the control unit is further to program the memory cell using an initial sequence of electrical pulses, wherein the initial sequence comprises a set pulse and the electrical pulse comprising the quenching period including the initial portion and the subsequent portion. ### Claim 15 (depends on 14) The memory device of claim 14, wherein the control unit is further to program the memory cell with a staircase up sequence of electrical pulses. ### Claim 16 (depends on 11) The memory device of claim 11, wherein the memory cells comprise multi-level memory cells. ### Claim 17 A system, comprising: a processor to generate a memory access command; and a memory device comprising a plurality of memory cells, wherein the memory device is communicatively coupled to the processor; the memory device to program a memory cell of the plurality of memory cells with a sequence of electrical pulses at least in part in response to receiving the memory access command, wherein the sequence comprises a set electrical pulse, and wherein the sequence also comprises an electrical pulse, wherein a fall time of an initial portion of a quenching period of the electrical pulse is less than a fall time of a subsequent portion of the quenching period. ### Claim 18 (depends on 17) The system of claim 17, wherein the memory device is to select the subsequent portion based at least in part on a target programmed state specified at least in part by the memory access command. ### Claim 19 (depends on 17) The system of claim 17, wherein the plurality of memory cells comprises multi-level memory cells.