# US 8,787,092 B2 · Programming inhibit method of nonvolatile memory apparatus for reducing leakage current

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- Number: US 8,787,092 B2
- Document ID: US8787092B2
- Status: Granted
- Kind: B2
- Application number: 13/418,352
- Filed: 2012-03-13
- Published: 2013-09-19
- Granted: 2014-07-22
- Earliest claimed: 2012-03-13
- Assignees: eMemory Technology Inc.
- Applicants: Wei-Ren Chen; Te-Hsun Hsu; Hsin-Ming Chen
- Inventors: Wei-Ren Chen; Te-Hsun Hsu; Hsin-Ming Chen
- Web page: https://patentgrep.com/patent/US8787092B2

## CPC

- G11C 16/10: Programming or data input circuits
- G11C 16/0433: {comprising cells containing a single floating gate transistor and one or more separate select transistors}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The invention provides a nonvolatile memory apparatus. The nonvolatile memory apparatus comprises a plurality of memory cells and a signal generator. The memory cells are arranged in an array, and each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal. The signal generator is coupled to the memory cells. When the nonvolatile memory apparatus executes a programming operation, the signal generator provides a programming signal to the control gate terminals of a plurality of inhibited memory cells among the memory cells. Wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage.

## Claims

### Claim 1

A nonvolatile memory apparatus, comprising:
a plurality of memory cells, the plurality of memory cells are arranged in an array, each of the memory cells has a control gate terminal, a floating gate, a source line terminal, a bit-line terminal, a selected gate terminal and a word-line terminal, wherein each of the memory cells is configured as a structure of three transistors and one capacitor (3T1C), and the floating gate is a single-poly gate; and
a signal generator, coupled to the memory cells, when the nonvolatile memory apparatus executing a programming operating, the signal generator providing a programming signal to the control gate terminals of the memory cells,
wherein, the programming signal is a pulse signal with a direct-current (DC) offset voltage, when the nonvolatile memory apparatus executing the programming process, the signal generator further providing a first and a second bit-line signals to the bit-line terminals of the inhibited and non-inhibited memory cells respectively, wherein, the voltage level of the first bit-line signal is larger than the second bit-line signal.

### Claim 2 (depends on 1)

The nonvolatile memory apparatus according to claim 1, wherein the source line terminals of the memory cells are coupled to a plurality of source signals respectively, the word-line terminals of the memory cells are coupled to a plurality of word line signals respectively, and the selected gate terminals of the memory cells are coupled to a plurality of selected gate signals respectively.

### Claim 3 (depends on 2)

The nonvolatile memory apparatus according to claim 2, wherein the voltage level of each of the source signals is equal to or greater than 0 volt.

### Claim 4 (depends on 1)

The nonvolatile memory apparatus according to claim 1, wherein each of the memory cells comprises:
a first transistor, having a first terminal, a second terminal and a first control terminal, the first terminal of the first transistor is coupled to the source line terminal, the first control terminal of the first transistor is coupled to the selected gate terminal;
a boosting capacitor, having a third terminal and a fourth terminal, the third terminal of the boosting capacitor is coupled to the control gate terminal;
a second transistor, having a fifth terminal, a sixth terminal and a second control terminal, the fifth terminal of the second transistor is coupled to the second terminal of the first transistor, the second control terminal of the second transistor is coupled to the fourth terminal of the boosting capacitor and serves as the floating gate; and
a third transistor, having a seventh terminal, an eighth terminal and a third control terminal, the seventh terminal of the third transistor is coupled to the sixth terminal of the second transistor, the third control terminal of the third transistor is coupled to the word-line terminal, the eighth terminal of the third transistor is coupled to the bit-line terminal.

### Claim 5 (depends on 1)

The nonvolatile memory apparatus according to claim 1, wherein the DC offset voltage is larger than 0 volt.

### Claim 6 (depends on 1)

The nonvolatile memory apparatus according to claim 1, wherein the pulse signal is a periodical signal.