# US 8,787,091 B2 · Nonvolatile semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,091 B2 - Document ID: US8787091B2 - Status: Granted - Kind: B2 - Application number: 14/066,875 - Filed: 2013-10-30 - Published: 2014-02-20 - Granted: 2014-07-22 - Earliest claimed: 2009-09-16 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Kabushiki Kaisha Toshiba - Inventors: Yasuhiro Shiino; Eietsu Takahashi - Web page: https://patentgrep.com/patent/US8787091B2 ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 11/5635: {Erasing circuits} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/10: Programming or data input circuits - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C 16/28: using differential sensing or reference cells, e.g. dummy cells - G11C 16/3404: {Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells} - G11C 16/3413: {Circuits or methods to recover overprogrammed nonvolatile memory cells detected during program verification, usually by means of a "soft" erasing step} - G11C 16/344: {Arrangements for verifying correct erasure or for detecting overerased cells} - G11C 16/3445: {Circuits or methods to verify correct erasure of nonvolatile memory cells} - G11C 16/3463: {Circuits or methods to detect overprogrammed nonvolatile memory cells, usually during program verification} - G11C 2211/5621: Multilevel programming verification - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line. ## Claims ### Claim 1 A nonvolatile semiconductor memory device, comprising a memory cell array configured as an arrangement of NAND cell units each including a memory string and select transistors connected to both ends of the memory string respectively, the memory string including a plurality of nonvolatile memory cells connected in series; word lines connected to control gate electrodes of the nonvolatile memory cells; bit lines connected to first ends of the NAND cell units; a source line connected to second ends of the NAND cell units; and a control circuit configured to perform a pre-program operation before an erasing operation for the NAND cell units arranged in a block, the NAND cell units that share the word lines forming the block, the control circuit being configured to execute the erasing operation by applying an erasing voltage to the NAND cell units in the block, and to execute the pre-program operation by applying a certain pre-program voltage to first nonvolatile memory cells in the NAND cell units, and by applying a voltage different from the certain pre-program voltage to second nonvolatile memory cells in the NAND cell units, the second nonvolatile memory cells including at least nonvolatile memory cells at the both ends of the memory string. ### Claim 2 (depends on 1) The nonvolatile semiconductor memory device according to claim 1, wherein the certain pre-program voltage is applied to first word lines connected to the control gate electrodes of the first nonvolatile memory cells, and the voltage different from the certain pre-program voltage is applied to second word lines connected to the control gate electrodes of the second nonvolatile memory cells. ### Claim 3 (depends on 2) The nonvolatile semiconductor memory device according to claim 2, wherein among the nonvolatile memory cells, the nonvolatile memory cells provided at the both ends of the memory string are dummy cells which are not used for data storage, and the second word lines include dummy word lines connected to the control gate electrodes of the dummy cells. ### Claim 4 (depends on 2) The nonvolatile semiconductor memory device according to claim 2, wherein the certain pre-program voltage has a higher positive value than the voltage different from the certain pre-program voltage. ### Claim 5 (depends on 2) The nonvolatile semiconductor memory device according to claim 2, wherein the erasing voltage is simultaneously applied to the first nonvolatile memory cells and the second nonvolatile memory cells. ### Claim 6 (depends on 5) The nonvolatile semiconductor memory device according to claim 5, wherein a positive boosted voltage as the erasing voltage is applied to a well in which both the first nonvolatile memory cells and the second nonvolatile memory cells are formed. ### Claim 7 (depends on 1) The nonvolatile semiconductor memory device according to claim 1, wherein the control circuit is configured to perform a writing operation for the NAND cell units and to be capable of varying a voltage value applied to the NAND cell units based on number of times the writing operation or the erasing operation has been performed. ### Claim 8 (depends on 7) The nonvolatile semiconductor memory device according to claim 7, wherein the control circuit is configured to be capable of varying a voltage value applied to at least one of the word lines connected to the control gate electrodes of the nonvolatile memory cells based on number of times the writing operation or the erasing operation has been performed. ### Claim 9 (depends on 1) The nonvolatile semiconductor memory device according to claim 1, wherein the first nonvolatile memory cells are configured to be capable of storing multi-bit data. ### Claim 10 A nonvolatile semiconductor memory device, comprising a memory cell array configured as an arrangement of NAND cell units each including a memory string and select transistors connected to both ends of the memory string respectively, the memory string including a plurality of nonvolatile memory cells connected in series; word lines connected to control gate electrodes of the nonvolatile memory cells; bit lines connected to first ends of the NAND cell units; a source line connected to second ends of the NAND cell units; and a control circuit configured to perform a pre-program operation before an erasing operation for the NAND cell units arranged in a block, the NAND cell units that share the word lines forming the block, the control circuit being configured to execute the erasing operation by applying an erasing voltage to the NAND cell units in the block, and to execute the pre-program operation by applying a first gate voltage to first nonvolatile memory cells in the NAND cell units, and by applying a second gate voltage different from the first gate voltage to second nonvolatile memory cells in the NAND cell units, the second nonvolatile memory cells including at least nonvolatile memory cells at the both ends of the memory string. ### Claim 11 (depends on 10) The nonvolatile semiconductor memory device according to claim 10, wherein the first gate voltage is applied to first word lines connected to the control gate electrodes of the first nonvolatile memory cells, and the second gate voltage is applied to second word lines connected to the control gate electrodes of the second nonvolatile memory cells. ### Claim 12 (depends on 11) The nonvolatile semiconductor memory device according to claim 11, wherein among the nonvolatile memory cells, the nonvolatile memory cells provided at the both ends of the memory string are dummy cells which are not used for data storage, and the second word lines include dummy word lines connected to the control gate electrodes of the dummy cells. ### Claim 13 (depends on 11) The nonvolatile semiconductor memory device according to claim 11, wherein the first gate voltage has a higher positive value than the second gate voltage. ### Claim 14 (depends on 11) The nonvolatile semiconductor memory device according to claim 11, wherein the erasing voltage is simultaneously applied to the first nonvolatile memory cells and the second nonvolatile memory cells. ### Claim 15 (depends on 14) The nonvolatile semiconductor memory device according to claim 14, wherein a positive boosted voltage as the erasing voltage is applied to a well in which both the first nonvolatile memory cells and the second nonvolatile memory cells are formed. ### Claim 16 (depends on 14) The nonvolatile semiconductor memory device according to claim 14, wherein the control circuit is configured to perform a writing operation for the NAND cell units and to be capable of varying a voltage value applied to the NAND cell units based on number of times the writing operation or the erasing operation has been performed. ### Claim 17 (depends on 16) The nonvolatile semiconductor memory device according to claim 16, wherein the control circuit is configured to be capable of varying a voltage value applied to at least one of the word lines connected to the control gate electrodes of the nonvolatile memory cells based on number of times the writing operation or the erasing operation has been performed. ### Claim 18 (depends on 10) The nonvolatile semiconductor memory device according to claim 10, wherein the first nonvolatile memory cells are configured to be capable of storing multi-bit data.