# US 8,787,090 B2 · Memory cell operation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,090 B2 - Document ID: US8787090B2 - Status: Granted - Kind: B2 - Application number: 13/372,669 - Filed: 2012-02-14 - Published: 2012-06-07 - Granted: 2014-07-22 - Earliest claimed: 2007-10-22 - Assignees: Micron Technology, Inc. - Applicants: Akira Goda; Seiichi Aritome - Inventors: Akira Goda; Seiichi Aritome - Web page: https://patentgrep.com/patent/US8787090B2 ## CPC - G11C 16/3468: {Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Embodiments of the present disclosure provide methods, devices, modules, and systems for programming memory cells. One method includes determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state, and adjusting at least one operating parameter associated with programming the group of memory cells at least partially based on the determined quantity of erase pulses. ## Claims ### Claim 1 A memory device comprising: an array of memory cells; and a controller coupled to the array and configured to: track a quantity of erase pulses used to place a number of memory cells of the array in an erased state; and adjust at least one operating parameter associated with programming the number of memory cells at a number of particular intervals based, at least partially, on the quantity of erase pulses; and wherein the at least one operating parameter includes at least one of: a program start voltage; a program step voltage; and a pass-through voltage. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the controller is further configured to program the number of memory cells using at least one adjusted operating voltage. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the controller is configured to: count the quantity of erase pulses used to place the number of memory cells in the erased state; identify a range of program/erase processing cycles corresponding to the quantity of erase pulses; and adjust a number of operating parameters associated with the range. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the at least one operating parameter adjusted by the controller includes at least two of: the program start voltage; the pass-through voltage; and the program step voltage. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the controller is configured to: maintain the at least one operating parameter at an initial level when the quantity of erase pulses is at or below a first quantity; and adjust the at least one operating parameter when the quantity of erase pulses is at or exceeds each of a number of thresholds. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the number of thresholds is at least two and wherein the controller is configured to: adjust the at least one operating parameter to a first adjusted level when the quantity of erase pulses reaches or exceeds a first threshold; and adjust the at least one operating parameter to second adjusted level when the quantity of erase pulses reaches or exceeds a second threshold. ### Claim 7 (depends on 6) The memory device of claim 6, wherein the second threshold is greater than the first threshold. ### Claim 8 A memory device comprising: an array of memory cells; and a controller coupled to the array and configured to: determine a quantity of erase pulses used to place a number of memory cells of the array in an erased state; and adjust, from an initial level to one of at least two different adjusted levels, at least one operating parameter associated with programming the number of memory cells based, at least partially, on the quantity of erase pulses; wherein a first of the at least two different adjusted levels corresponds to a first threshold quantity of erase pulses and a second of the at least two different adjusted levels corresponds to a second threshold quantity of erase pulses; and wherein the at least one operating parameter includes at least one of: a program start voltage; a program step voltage; and a pass-through voltage. ### Claim 9 A method for operating an array of memory cells, the method comprising: determining a quantity of erase pulses used to place a group of memory cells of the array in an erased state; and adjusting, from an initial level to an adjusted level, at least one operating parameter associated with programming the group of memory cells at least partially based on the quantity of erase pulses; wherein the at least one operating parameter includes at least one of: a program start voltage; a program step voltage; and a pass-through voltage. ### Claim 10 (depends on 9) The method of claim 9, wherein the method includes programming the group of memory cells using the adjusted level for the at least one operating parameter. ### Claim 11 (depends on 9) The method of claim 9, wherein adjusting includes: maintaining the at least one operating parameter at the initial level when the quantity of erase pulses is below a first quantity; adjusting one or more of the at least one operating parameter to the adjusted level when the quantity of erase pulses is between the first quantity and a second quantity; and adjusting one or more of the at least one operating parameter to a different adjusted level when the quantity of erase pulses is greater than the second quantity. ### Claim 12 (depends on 9) The method of claim 9, wherein the method includes determining the quantity of erase pulses by counting the quantity of erase pulses. ### Claim 13 (depends on 9) The method of claim 9, wherein adjusting includes decreasing the magnitude of at least one of: the program start voltage; the program step voltage; and the pass-through voltage. ### Claim 14 (depends on 9) The method of claim 9, wherein adjusting includes increasing the at least one operating voltage associated with programming the group of memory cells. ### Claim 15 (depends on 14) The method of claim 14, wherein increasing the at least one operating voltage includes increasing a program verify voltage associated with programming the group of memory cells. ### Claim 16 (depends on 9) The method of claim 9, wherein adjusting includes adjusting the magnitudes of each of: the program start voltage; the program step voltage; and the pass-through voltage. ### Claim 17 A method for operating an array of memory cells, the method comprising: counting a quantity of erase pulses used to place a number of memory cells of the array in an erased state; and changing, from an initial voltage to an adjusted voltage, at least one operating voltage associated with programming the number of memory cells based, at least partially, on the quantity of erase pulses; and wherein the at least one operating voltage includes at least one of: a program start voltage; a program step voltage; and a pass-through voltage. ### Claim 18 (depends on 17) The method of claim 17, wherein changing includes decreasing the program start voltage and decreasing the pass-through voltage associated with programming the number of memory cells. ### Claim 19 (depends on 17) The method of claim 17, including: estimating a quantity of program/erase cycles performed on the number of memory cells based on the quantity of erase pulses used to place the number of memory cells in the erased state; and changing the at least one operating voltage from the initial voltage to the adjusted voltage when the quantity of program/erase cycles reaches or exceeds a threshold quantity. ### Claim 20 (depends on 17) The method of claim 17, including adjusting a maximum erase pulse magnitude associated with erasing the number of memory cells based on the quantity of erase pulses.