# US 8,787,089 B2 · Semiconductor device and method of controlling the same

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- Number: US 8,787,089 B2
- Document ID: US8787089B2
- Status: Granted
- Kind: B2
- Application number: 13/692,736
- Filed: 2012-12-03
- Published: 2013-04-18
- Granted: 2014-07-22
- Earliest claimed: 2005-12-15
- Assignees: Spansion LLC
- Applicants: Spansion LLC
- Inventors: Masaru Yano; Kazuhide Kurosaki; Mototada Sakashita
- Web page: https://patentgrep.com/patent/US8787089B2

## CPC

- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/0491: {Virtual ground arrays}
- G11C 16/30: Power supply circuits
- G11C 5/02: Disposition of storage elements, e.g. in the form of a matrix array
- G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C 7/18: Bit line organisation; Bit line lay-out
- G11C 16/0408: {comprising cells containing floating gate transistors (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/24: Bit-line control circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

An embodiment of the invention provides a semiconductor device that includes: a memory cell array that includes non-volatile memory cells; a first selecting circuit that connects or disconnects a source and a drain of a transistor that forms one of the memory cells, to or from a data line DATAB connected to a first power supply; and a second selecting circuit that connects or disconnects the source and drain to or from a ground line ARVSS connected to a second power supply. In this semiconductor device, the first selecting circuit and the second selecting circuit are arranged on the opposite sides of the memory cell array. One embodiment of the invention also provides a method of controlling the semiconductor device.

## Claims

### Claim 1

A method of controlling a semiconductor device that comprises: a memory cell array that comprises non-volatile memory cells; a first power supply and a second power supply that apply voltage to bit lines connected to sources and drains of transistors that form the memory cells; a first storage unit that stores first selecting information that indicates whether the bit lines are to be connected to the first power supply; and a second storage unit that stores second selecting information that indicates whether the bit lines are to be connected to the second power supply,
the method comprising:
connecting the first storage unit and the second storage unit to the bit lines; and
transferring the first selecting information from the first storage unit to the second storage unit via the bit lines.

### Claim 2 (depends on 1)

The method of claim 1, wherein the non-volatile memory cells are virtual ground memory cells.

### Claim 3 (depends on 1)

The method of claim 1, wherein the semiconductor device is flash memory.

### Claim 4 (depends on 1)

The method of claim 1, wherein the semiconductor device is NOR flash memory.

### Claim 5 (depends on 1)

The method of claim 1, wherein the semiconductor device is NAND flash memory.

### Claim 6 (depends on 1)

The method of claim 1, wherein the semiconductor device further comprises:
a control circuit that performs said connecting.

### Claim 7 (depends on 1)

The method of claim 1, wherein the semiconductor device further comprises:
a control circuit that performs said transferring.

### Claim 8

A method of controlling a semiconductor device that comprises: a memory cell array that comprises non-volatile memory cells; a first power supply and a second power supply that apply voltage to bit lines connected to sources and drains of transistors that form the memory cells; a first storage unit that stores first selecting information that indicates whether the bit lines are to be connected to the first power supply; and a second storage unit that stores second selecting information that indicates whether the bit lines are to be connected to the second power supply,
the method comprising:
connecting the first storage unit and the second storage unit to the bit lines; and
transferring the first selecting information from the first storage unit to the second storage unit via the bit lines,
wherein the non-volatile memory cells are virtual ground memory cells and the semiconductor device is flash memory.

### Claim 9 (depends on 8)

The method of claim 8, wherein the semiconductor device is NOR flash memory.

### Claim 10 (depends on 8)

The method of claim 8, wherein the semiconductor device is NAND flash memory.

### Claim 11 (depends on 8)

The method of claim 8, wherein the semiconductor device further comprises:
a control circuit that performs said connecting.

### Claim 12 (depends on 8)

The method of claim 8, wherein the semiconductor device further comprises:
a control circuit that performs said transferring.

### Claim 13

A method of controlling a semiconductor device that comprises: a memory cell array that comprises non-volatile memory cells; a first power supply and a second power supply that apply voltage to bit lines connected to sources and drains of transistors that form the memory cells; a first storage unit that stores first selecting information that indicates whether the bit lines are to be connected to the first power supply; and a second storage unit that stores second selecting information that indicates whether the bit lines are to be connected to the second power supply,
the method comprising:
connecting the first storage unit and the second storage unit to the bit lines; and
transferring the first selecting information from the first storage unit to the second storage unit via the bit lines,
wherein the semiconductor device further comprises a control circuit that performs said connecting.

### Claim 14 (depends on 13)

The method of claim 13, wherein the non-volatile memory cells are virtual ground memory cells.

### Claim 15 (depends on 13)

The method of claim 13, wherein the semiconductor device is flash memory.

### Claim 16 (depends on 13)

The method of claim 13, wherein the semiconductor device is NOR flash memory.

### Claim 17 (depends on 13)

The method of claim 13, wherein the semiconductor device is NAND flash memory.

### Claim 18 (depends on 13)

The method of claim 13, wherein the control circuit performs said transferring.