# US 8,787,083 B2 · Memory circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,083 B2 - Document ID: US8787083B2 - Status: Granted - Kind: B2 - Application number: 13/365,999 - Filed: 2012-02-03 - Published: 2012-08-16 - Granted: 2014-07-22 - Earliest claimed: 2011-02-10 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Masashi Fujita - Inventors: Masashi Fujita - Web page: https://patentgrep.com/patent/US8787083B2 ## CPC - G11C 11/40: using transistors - G11C 7/00: Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G11C 11/34: using semiconductor devices - G11C 14/00: Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down - G11C 14/0009: {in which the volatile element is a DRAM cell} - G11C 14/0054: {in which the volatile element is a SRAM cell} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - G11C 5/005: {Circuit means for protection against loss of information of semiconductor storage devices} - G11C 5/06: Arrangements for interconnecting storage elements electrically, e.g. by wiring - H10D 30/68: Floating-gate IGFETs - H10D 30/69: IGFETs having charge trapping gate insulators, e.g. MNOS transistors - G11C: STATIC STORES (semiconductor memory devices H10B) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract While the supply of power is stopped, a data signal that has been held in a volatile memory section can be held in a nonvolatile memory section. In the nonvolatile memory section, a transistor having an extremely low off-state current allows a data signal to be held in the capacitor for a long period of time. Thus, the nonvolatile memory section can hold the logic state even while the supply of power is stopped. When the supply of power is started again, the data signal that has been held in the capacitor while the supply of power has been stopped is set at such a potential that malfunction does not occur by turning on the reset circuit. ## Claims ### Claim 1 A semiconductor device comprising: a volatile memory section; and a nonvolatile memory section comprising: a first transistor; a second transistor; and a reset circuit, wherein a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor, and wherein the reset circuit is configured to input an electrical potential which turns off the second transistor to the gate of the second transistor. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the volatile memory section is configured to hold a data signal, and wherein the nonvolatile memory section is configured to hold the data signal while supply of power to the semiconductor device is stopped. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, further comprising a selector circuit, wherein a data input terminal of the volatile memory section is electrically connected to a data input terminal of the nonvolatile memory section, wherein a data output terminal of the volatile memory section and a data output terminal of the nonvolatile memory section are electrically connected to the selector circuit, and wherein the data input terminal of the nonvolatile memory section is electrically connected to the other of the source and the drain of the first transistor. ### Claim 4 (depends on 3) The semiconductor device according to claim 3, further comprising a third transistor and a fourth transistor, wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the data output terminal of the nonvolatile memory section, wherein a first control signal is inputted to the gate of the third transistor and the gate of the fourth transistor, and wherein a second control signal is inputted to the gate of the first transistor. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, further comprising a capacitor, wherein the capacitor is electrically connected to the gate of the second transistor. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the nonvolatile memory section is configured to hold a data signal between the one of the source and the drain of the first transistor and the gate of the second transistor while supply of power to the semiconductor device is stopped. ### Claim 7 (depends on 4) The semiconductor device according to claim 4, further comprising a switching circuit, wherein the switching circuit is configured to break electrical continuity between the data input terminal of the nonvolatile memory section and the other of the source and the drain of the first transistor. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the switching circuit comprises a logic circuit supplied with the first control signal and the second control signal, and an analog switch turned on or off by the logic circuit. ### Claim 9 (depends on 4) The semiconductor device according to claim 4, wherein the reset circuit comprises a logic circuit supplied with the first control signal and the second control signal, and an analog switch turned on or off by the logic circuit. ### Claim 10 (depends on 4) The semiconductor device according to claim 4, wherein the selector circuit comprises a logic circuit supplied with the first control signal and the second control signal, a first analog switch and a second analog switch. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the first transistor comprises a channel formation region comprising an oxide semiconductor. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the second transistor comprises a channel formation region comprising silicon. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the second transistor forms a layered structure with the first transistor. ### Claim 14 (depends on 1) A signal processing unit comprising: the semiconductor device according to claim 1; and an arithmetic unit transmitting and receiving data to/from the semiconductor device. ### Claim 15 A semiconductor device comprising: a flip-flop circuit; a selector circuit; a first transistor; a second transistor; a third transistor; a fourth transistor; a first switch; and a second switch, wherein an input terminal of the flip-flop circuit is electrically connected to one of a source and a drain of the first transistor through the first switch, wherein an output terminal of the flip-flop circuit is electrically connected to the selector circuit, wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor, wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor, wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor, wherein the other of the source and the drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor, wherein the other of the source and the drain of the third transistor is electrically connected to the selector circuit, and wherein the one of the source and the drain of the first transistor is electrically connected to the other of the source and the drain of the second transistor through the second switch. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, further comprising a capacitor, wherein the capacitor is electrically connected to the gate of the second transistor. ### Claim 17 (depends on 15) The semiconductor device according to claim 15, wherein a data signal is input to the input terminal of the flip-flop circuit, wherein a first control signal is input to the gate of the third transistor and the gate of the fourth transistor, wherein a second control signal is input to the gate of the first transistor, wherein the first switch is controlled by the first control signal and the second control signal, and wherein the second switch is controlled by the first control signal and the second control signal. ### Claim 18 (depends on 15) The semiconductor device according to claim 15, wherein the first transistor comprises a channel formation region comprising an oxide semiconductor. ### Claim 19 (depends on 15) The semiconductor device according to claim 15, wherein the second transistor comprises a channel formation region comprising silicon. ### Claim 20 (depends on 15) The semiconductor device according to claim 15, wherein the second transistor forms a layered structure with the first transistor. ### Claim 21 (depends on 15) A central processing unit comprising: the semiconductor device according to claim 15, and an arithmetic logic unit transmitting and receiving data to/from the semiconductor device.