# US 8,787,074 B2 · Static random access memory test structure > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,074 B2 - Document ID: US8787074B2 - Status: Granted - Kind: B2 - Application number: 13/273,271 - Filed: 2011-10-14 - Published: 2013-04-18 - Granted: 2014-07-22 - Earliest claimed: 2011-10-14 - Assignees: International Business Machines Corporation - Applicants: Oliver D. Patterson; Jin Zheng Wallner; Thomas A. Wallner; Shenzhi Yang - Inventors: Oliver D. Patterson; Jin Zheng Wallner; Thomas A. Wallner; Shenzhi Yang - Web page: https://patentgrep.com/patent/US8787074B2 ## CPC - G11C 29/50008: {of impedance} - G11C 11/41: forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger - G11C 2029/0403: {during or with feedback to manufacture} - G11C 2029/5002: {Characteristic} - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A static random access memory (SRAM) test structure includes a p-type source/drain implant region comprising contacts (CAs), wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of Vdd CAs and rectangular contacts (CArecs), and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region. ## Claims ### Claim 1 A static random access memory (SRAM) test structure, comprising: a p-type source/drain implant region comprising contacts (CAs) located in the p-type source/drain implant region, wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs in the SRAM test structure, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of Vdd CAs and rectangular contacts (CArecs), wherein a CArec simultaneously contacts a gate line and a source/drain, and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region. ### Claim 2 (depends on 1) The SRAM test structure of claim 1, wherein there is not a well under the p-type source/drain implant region. ### Claim 3 (depends on 1) The SRAM test structure of claim 1, wherein there is a p-well under the p-type source/drain implant region. ### Claim 4 (depends on 1) The SRAM test structure of claim 1, wherein the ungrounded region comprises one of an n-type source/drain implant region and an undoped region. ### Claim 5 (depends on 1) The SRAM test structure of claim 1, wherein the p-type source/drain implant region further comprises a second plurality of CArecs and Vdd CAs. ### Claim 6 (depends on 1) The SRAM test structure of claim 1, wherein a topology of the SRAM test structure, comprising shallow trench isolation (STI) regions and spacer shape, in the p-type source/drain implant region is determined by one of a Boolean method or a custom layer method. ### Claim 7 (depends on 1) The SRAM test structure of claim 1, wherein the short comprises a short between a CA in the p-type source/drain implant region and a CA not located in the p-type source/drain implant region, and in the event a CArec not located in the p-type source/drain implant region that contacts a gate line that is also contacted by the CA not located in the p-type source/drain implant region is grounded, the short is a contact-to-gate line short; and otherwise the short is a subway in a contact dielectric layer of the SRAM test structure. ### Claim 8 (depends on 7) The SRAM test structure of claim 7, wherein the CA not located in the p-type source/drain implant region comprises a Vdd contact. ### Claim 9 (depends on 1) The SRAM test structure of claim 1, wherein the short comprises a short between a CA in the p-type source/drain implant region and a CA not located in the p-type source/drain implant region, and in the event a word line CA that contacts a gate line that is also contacted by the CA not located in the p-type source/drain implant region is grounded, the short is a contact-to-gate line short; and otherwise the short is a subway in a contact dielectric layer of the SRAM test structure. ### Claim 10 (depends on 9) The SRAM test structure of claim 9, wherein the CA not located in the p-type source/drain implant region comprises one of a bit line contact and a node contact. ### Claim 11 (depends on 1) The SRAM test structure of claim 1, wherein the short comprises a short between a CA in the p-type source/drain implant region and a first CArec not located in the p-type source/drain implant region, and in the event a second CArec not located in the p-type source/drain implant region that contacts a gate line that is also contacted by the first CArec not located in the p p-type source/drain implant region is grounded, the short is a contact-to-gate line short; and otherwise the short is a subway in a contact dielectric layer of the SRAM test structure. ### Claim 12 (depends on 11) The SRAM test structure of claim 11, wherein the inspection comprises e-beam inspection. ### Claim 13 A method for short detection using SRAM test structure, comprising: inspecting the SRAM test structure to detect the presence of a short, wherein the SRAM test structure comprises: a p-type source/drain implant region comprising contacts (CAs) located in the p-type source/drain implant region, wherein the CAs in the p-type source/drain implant region comprise a first plurality of bit line, ground, and node CAs in the SRAM test structure, and wherein the CAs in the p-type source/drain implant region are grounded during an inspection of the SRAM test structure; and an ungrounded region, the ungrounded region being distinct from the p-type source/drain implant region and being ungrounded during the inspection of the SRAM test structure, the ungrounded region comprising contacts (CAs) and rectangular contacts (CArecs) comprising a second plurality of bit line, ground, and node CAs, and further comprising a first plurality of Vdd CAs and rectangular contacts (CArecs), wherein a CArec simultaneously contacts a gate line and a source/drain, and wherein a CA or CArec in the ungrounded region is grounded during the inspection in the event of a short to a CA in the p-type source/drain implant region; and determining whether the detected short comprises a subway in a contact dielectric layer of the SRAM test structure or a contact-to-gate line short based on the inspection. ### Claim 14 (depends on 13) The method of claim 13, wherein there is not an n-well under the p-type source/drain implant region. ### Claim 15 (depends on 13) The method of claim 13, wherein the ungrounded region comprises one of a n-type source/drain implant region and an undoped region. ### Claim 16 (depends on 13) The method of claim 13, wherein the p-type source/drain implant region further comprises a second plurality of CArecs and Vdd CAs. ### Claim 17 (depends on 13) The method of claim 13, wherein the short comprises a short between a CA in the p-type source/drain implant region and a CA not located in the p-type source/drain implant region, and in the event a CArec not located in the p-type source/drain implant region that contacts a gate line that is also contacted by the CA not located in the p-type source/drain implant region is grounded, the short is a contact-to-gate line short; and otherwise the short is a subway in a contact dielectric layer of the SRAM test structure. ### Claim 18 (depends on 17) The method of claim 17, wherein the CA not located in the p-type source/drain implant region comprises a Vdd contact. ### Claim 19 (depends on 13) The method of claim 13, wherein the short comprises a short between a CA in the p-type source/drain implant region and a CA not located in the p-type source/drain implant region, and in the event a word line CA that contacts a gate line that is also contacted by the CA not located in the p-type source/drain implant region is grounded, the short is a contact-to-gate line short; and otherwise the short is a subway in a contact dielectric layer of the SRAM test structure, wherein the CA not located in the p-type source/drain implant region comprises one of a bit line contact and a node contact. ### Claim 20 (depends on 13) The method of claim 13, wherein the short comprises a short between a CA in the p-type source/drain implant region and a first CArec not located in the p-type source/drain implant region, and in the event a second CArec not located in the p-type source/drain implant region that contacts a gate line that is also contacted by the first CArec not located in the p p-type source/drain implant region is grounded, the short is a contact-to-gate line short; and otherwise the short is a subway in a contact dielectric layer of the SRAM test structure.