# US 8,787,072 B2 · Floating-body/gate DRAM cell

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,787,072 B2
- Document ID: US8787072B2
- Status: Granted
- Kind: B2
- Application number: 13/124,066
- Filed: 2009-12-29
- Published: 2011-09-15
- Granted: 2014-07-22
- Earliest claimed: 2007-10-01
- Assignees: University of Florida Research Foundation, Inc.
- Applicants: Jerry G. Fossum; Zhichao Lu
- Inventors: Jerry G. Fossum; Zhichao Lu
- Web page: https://patentgrep.com/patent/US8787072B2

## CPC

- H10B 12/20: {DRAM devices comprising floating-body transistors, e.g. floating-body cells}
- G11C 11/404: with one charge-transfer gate, e.g. MOS transistor, per cell
- H10D 12/211: {Gated diodes}
- H10D 30/711: {having floating bodies}
- G11C 2211/4016: Memory devices with silicon-on-insulator cells
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Memory cell structures and biasing schemes are provided. Certain embodiments pertain to a modified floating-body gate cell, which can provide improved retention times. In one embodiment, a gated diode is used to drive the gate of a second transistor structure of a cell. In another embodiment, a body-tied-source (BTS) field effect transistor is used to drive the gate of the second transistor structure of a cell.

## Claims

### Claim 1

A dynamic memory comprising:
a first transistor structure having a first gate, a first drain connected to a first bit line, a first source, and a first body, wherein the first source is tied to the first body; and
a second transistor structure having a second gate coupled to the first body that is tied to the first source, a second source connected to a ground, and a second drain connected to a second bit line.

### Claim 2 (depends on 1)

The dynamic memory according to claim 1, wherein the first gate is connected to a word line such that the first transistor structure charges and discharges the second gate by using channel current of the first transistor structure.

### Claim 3

A dynamic memory cell, comprising:
a first gate electrode on a gate insulating layer on a p-type region of a substrate, the first gate electrode being connected to a word line;
a first n+ drain region at one side of the p-type region in the substrate, the first n+ drain region being connected to a first bit line;
a first n+ source region in the substrate at an opposite side of the p-type region from the first n+ drain region;
a p+ region extending from the p-type region at the opposite side of the p-type region adjacent the first n+ source region, the p+ region providing a contact region for electrical connection to the p-type region;
a second gate electrode on a second gate insulating layer, wherein the n+ source region and the p+ region are tied together and connected to the second gate electrode;
a second n+ drain region at a side of the gate electrode, the second n+ drain region being connected to a second bit line; and
a second n+ source region at another side of the gate electrode, the second n+ source region being connected to a ground.

### Claim 4 (depends on 3)

The dynamic memory cell according to claim 3, wherein the first gate electrode is disposed having an underlap with at least one of the first n+ drain region and the first n+ source region.