# US 8,787,070 B2 · Reference cell circuit and variable resistance nonvolatile memory device including the same

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- Number: US 8,787,070 B2
- Document ID: US8787070B2
- Status: Granted
- Kind: B2
- Application number: 13/634,292
- Filed: 2012-04-12
- Published: 2013-02-21
- Granted: 2014-07-22
- Earliest claimed: 2011-04-13
- Assignees: Panasonic Corporation
- Applicants: Kazuhiko Shimakawa
- Inventors: Kazuhiko Shimakawa
- Web page: https://patentgrep.com/patent/US8787070B2

## CPC

- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0009: {RRAM elements whose operation depends upon chemical change}
- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0064: {Verifying circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Included are reference cells each including a variable resistance element which reversibly changes between a predetermined low resistance state LR and a predetermined high resistance state HR according to an application of an electric signal, a comparator which compares resistance values of the reference cells, a pulse generation circuit which generates an electric signal for setting the reference cells to LR or HR, and a control circuit which controls operations where application of the generated electric signal to one of the reference cells corresponding to a comparison result of the comparator and application of a new electric signal generated by the pulse generation circuit to one of the reference cells corresponding to a new comparison result of the comparator are repeated, and then one of the reference cells corresponding to a final comparison result of the comparator is connected to an output terminal.

## Claims

### Claim 1

A reference cell circuit comprising:
a first reference cell and a second reference cell each of which includes a variable resistance element which reversibly changes between a low resistance state and a high resistance state according to an application of an electric signal, the low resistance state having a resistance value within a first range, and the high resistance state having a resistance value within a second range which has a lower limit value higher than an upper limit value of the first range;
a comparator which compares a resistance value of the first reference cell with a resistance value of the second reference cell;
a control circuit;
an application circuit which applies an electric signal to a reference cell that is one of the first reference cell and the second reference cell and that is selected by the control circuit, the electric signal being for setting the selected reference cell to a target state which is one of the low resistance state and the high resistance state; and
an output circuit which electrically connects, to an output terminal, a reference cell that is one of the first reference cell and the second reference cell and that is selected by the control circuit,
wherein the control circuit executes a comparison operation and a write operation one or more times, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to a target resistance value that is a lower limit value or an upper limit value of the target state, the comparison operation causing the comparator to perform the comparison, and the write operation causing the application circuit to apply the electric signal to a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value further from the target resistance value according to each result of the comparison by the comparator, and
after the write operation, the control circuit executes an output operation which causes the output circuit to electrically connect, to the output terminal, a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value closer to the target resistance value according to a result of the comparison by the comparator.

### Claim 2 (depends on 1)

The reference cell circuit according to claim 1, further comprising
a pulse generation circuit which generates the electric signal.

### Claim 3 (depends on 1)

The reference cell circuit according to claim 1,
wherein the application circuit applies, as the electric signal, a first pulse signal and a second pulse signal to the reference cell selected by the control circuit, the first pulse signal being for setting the first reference cell and the second reference cell to one of the low resistance state and the high resistance state which is different from the target state, and the second pulse signal being applied after the first pulse signal for setting the first reference cell and the second reference cell to the target state.

### Claim 4 (depends on 1)

The reference cell circuit according to claim 1,
wherein each of the first reference cell and the second reference cell includes the variable resistance element and a transistor connected in series.

### Claim 5 (depends on 1)

The reference cell circuit according to claim 1,
wherein each of the first reference cell and the second reference cell includes the variable resistance element and a diode connected in series.

### Claim 6 (depends on 1)

The reference cell circuit according to claim 1,
wherein the variable resistance element comprises tantalum oxide.

### Claim 7 (depends on 1)

The reference cell circuit according to claim 1,
wherein, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to an upper limit value of the low resistance state, the control circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell determined by the comparator to have a lower resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the low resistance state, and in the output operation, the control circuit causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell determined by the comparator to have a higher resistance value.

### Claim 8 (depends on 1)

The reference cell circuit according to claim 1,
wherein, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to a lower limit value of the low resistance state, the control circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell determined by the comparator to have a higher resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the low resistance state, and in the output operation, the control circuit causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell determined by the comparator to have a lower resistance value.

### Claim 9 (depends on 1)

The reference cell circuit according to claim 1,
wherein, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to an upper limit value of the high resistance state, the control circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell determined by the comparator to have a lower resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the high resistance state, and in the output operation, the control circuit causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell determined by the comparator to have a higher resistance value.

### Claim 10 (depends on 1)

The reference cell circuit according to claim 1,
wherein, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to a lower limit value of the high resistance state, the control circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell determined by the comparator to have a higher resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the high resistance state, and in the output operation, the control circuit causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell determined by the comparator to have a lower resistance value.

### Claim 11 (depends on 1)

The reference cell circuit according to claim 1, further comprising
an other set of the first reference cell, the second reference cell, the comparator, the application circuit, and the output circuit,
wherein the control circuit executes the write operation and the output operation one or more times for each set, and
the reference cell circuit further comprises:
a second comparator which compares the resistance values of the reference cells connected to the output terminals of the respective sets; and
a second output circuit which connects, to an output terminal, one of the reference cells connected to the output terminals of the respective sets according to a result of the comparison by the second comparator.

### Claim 12

A variable resistance nonvolatile memory device comprising:
a memory cell array which includes a plurality of memory cells arranged in rows and columns, each of the memory cells including a variable resistance element which reversibly changes between a low resistance state and a high resistance state according to an application of an electric signal, the low resistance state having a resistance value within a first range, the high resistance state having a resistance value within a second range which has a lower limit value higher than an upper limit value of the first range;
a reference circuit which includes at least one reference cell circuit, and generates a reference level for determining a resistance state of each of the memory cells with reference to a resistance value of a reference cell connected to an output terminal of the at least one reference cell circuit; and
a read circuit which determines whether each memory cell is in the low resistance state or in the high resistance state by comparing a signal level obtained from the memory cell with the reference level generated by the reference circuit,
wherein each of the at least one reference cell circuit includes:
a first reference cell and a second reference cell each of which includes a variable resistance element which reversibly changes between the low resistance state and the high resistance state according to an application of an electric signal;
a comparator which compares a resistance value of the first reference cell with a resistance value of the second reference cell;
a control circuit;
an application circuit which applies an electric signal to a reference cell that is one of the first reference cell and the second reference cell and that is selected by the control circuit, the electric signal being for setting the selected reference cell to a target state which is one of the low resistance state and the high resistance state; and
an output circuit which electrically connects, to an output terminal, a reference cell that is one of the first reference cell and the second reference cell and that is selected by the control circuit,
wherein the control circuit executes a comparison operation and a write operation one or more times, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to a target resistance value that is a lower limit value or an upper limit value of the target state, the comparison operation causing the comparator to perform the comparison, and the write operation causing the application circuit to apply the electric signal to a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value further from the target resistance value according to each result of the comparison by the comparator, and
after the write operation, the control circuit executes an output operation which causes the output circuit to electrically connect, to the output terminal, a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value closer to the target resistance value according to a result of the comparison by the comparator.

### Claim 13 (depends on 12)

The variable resistance nonvolatile memory device according to claim 12,
wherein the reference circuit includes, as the at least one reference cell circuit, a first reference cell circuit and a second reference cell circuit,
wherein, (i) to make the resistance value of the first reference cell or the resistance value of the second reference cell included in the first reference cell circuit close to an upper limit value of the low resistance state, a control circuit included in the first reference cell circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell included in the first reference cell circuit and determined by the comparator to have a lower resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the low resistance state, and in the output operation, causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell included in the first reference cell circuit and determined by the comparator to have a higher resistance value, or
(ii) to make the resistance value of the first reference cell or the resistance value of the second reference cell included in the first reference cell circuit close to a lower limit value of the low resistance state, the control circuit included in the first reference cell circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell included in the first reference cell circuit and determined by the comparator to have a higher resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the low resistance state, and in the output operation, causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell included in the first reference cell circuit and determined by the comparator to have a lower resistance value, and
wherein, (i) to make the resistance value of the first reference cell or the resistance value of the second reference cell included in the second reference cell circuit close to an upper limit value of the high resistance state, a control circuit included in the second reference cell circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell included in the second reference cell circuit and determined by the comparator to have a lower resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the high resistance state, and in the output operation, causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell included in the second reference cell circuit and determined by the comparator to have a higher resistance value, or
(ii) to make the resistance value of the first reference cell or the resistance value of the second reference cell included in the second reference cell circuit close to a lower limit value of the high resistance state, the control circuit included in the second reference cell circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell included in the second reference cell circuit and determined by the comparator to have a higher resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the high resistance state, and in the output operation, causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell included in the second reference cell circuit and determined by the comparator to have a lower resistance value.

### Claim 14 (depends on 13)

The variable resistance nonvolatile memory device according to claim 13,
wherein, to make the resistance value of the first reference cell or the resistance value of the second reference cell included in the first reference cell circuit close to an upper limit value of the low resistance state, the control circuit included in the first reference cell circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell included in the first reference cell circuit and determined by the comparator to have a lower resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the low resistance state, and in the output operation, causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell included in the first reference cell circuit and determined by the comparator to have a higher resistance value,
wherein, to make the resistance value of the first reference cell or the resistance value of the second reference cell included in the second reference cell circuit close to a lower limit value of the high resistance state, the control circuit included in the second reference cell circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell included in the second reference cell circuit and determined by the comparator to have a higher resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the high resistance state, and in the output operation, causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell included in the second reference cell circuit and determined by the comparator to have a lower resistance value, and
wherein the reference circuit generates a reference level corresponding to an intermediate resistance value between a resistance value of the reference cell connected to the output terminal of the first reference cell circuit and a resistance value of the reference cell connected to the output terminal of the second reference cell circuit.

### Claim 15

A variable resistance nonvolatile memory device comprising:
a memory cell array including a plurality of memory cells arranged in rows and columns, each of the memory cells including a variable resistance element which reversibly changes between a low resistance state and a high resistance state according to an application of an electric signal, the low resistance state having a resistance value within a first range, the high resistance state having a resistance value within a second range which has a lower limit value higher than an upper limit value of the first range;
a refresh command circuit which includes a reference cell circuit, and outputs a refresh command signal when a resistance value of a reference cell connected to an output terminal of the reference cell circuit becomes a predetermined value; and
a control circuit which performs a read operation and then a refresh operation on at least a part of the memory cells in the memory cell array when the refresh command signal is output, the read operation being for reading data from the part of the memory cells, and the refresh operation being for rewriting the read data to the part of the memory cells,
wherein the reference cell circuit includes:
a first reference cell and a second reference cell each of which includes a variable resistance element which reversibly changes between the low resistance state and the high resistance state according to an application of an electric signal;
a comparator which compares a resistance value of the first reference cell with a resistance value of the second reference cell;
a control circuit;
an application circuit which applies an electric signal to a reference cell that is one of the first reference cell and the second reference cell and that is selected by the control circuit, the electric signal being for setting the selected reference cell to a target state which is one of the low resistance state and the high resistance state; and
an output circuit which electrically connects, to an output terminal, a reference cell that is one of the first reference cell and the second reference cell and that is selected by the control circuit,
wherein the control circuit executes a comparison operation and a write operation one or more times, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to a target resistance value that is a lower limit value or an upper limit value of the target state, the comparison operation causing the comparator to perform the comparison, and the write operation causing the application circuit to apply the electric signal to a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value further from the target resistance value according to each result of the comparison by the comparator, and
after the write operation, the control circuit executes an output operation which causes the output circuit to electrically connect, to the output terminal, a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value closer to the target resistance value according to a result of the comparison by the comparator.

### Claim 16 (depends on 15)

The variable resistance nonvolatile memory device according to claim 15,
wherein, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to an upper limit value of the low resistance state, the control circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell determined by the comparator to have a lower resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the low resistance state, and in the output operation, the control circuit causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell determined by the comparator to have a higher resistance value, and
the refresh command circuit outputs the refresh command signal when the resistance value of the reference cell connected to the output terminal of the reference cell circuit increases to a predetermined value.

### Claim 17 (depends on 15)

The variable resistance nonvolatile memory device according to claim 15,
wherein, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to a lower limit value of the high resistance state, the control circuit causes, for each write operation, the application circuit to apply, to one of the first reference cell and the second reference cell determined by the comparator to have a higher resistance value, an electric signal for setting the determined one of the first reference cell and the second reference cell to the high resistance state, and in the output operation, the control circuit causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell determined by the comparator to have a lower resistance value, and
the refresh command circuit outputs the refresh command signal when the resistance value of the reference cell connected to the output terminal of the reference cell circuit decreases to a predetermined value.

### Claim 18 (depends on 12)

The variable resistance nonvolatile memory device according to claim 12,
wherein, at a manufacturing process of the variable resistance nonvolatile memory device, the control circuit included in each of the at least one reference cell circuit executes the write operation in the reference cell circuit one or more times, and causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell corresponding to the result of the comparison by the comparator.

### Claim 19 (depends on 12)

The variable resistance nonvolatile memory device according to claim 12,
wherein, while the variable resistance nonvolatile memory device is in a standby state or an idle state, the control circuit included in each of the at least one reference cell circuit causes the application circuit to perform the write operation in the reference circuit one or more times, and causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell corresponding to the result of the comparison by the comparator.

### Claim 20 (depends on 15)

The variable resistance nonvolatile memory device according to claim 15,
wherein, when the refresh command signal is output, the control circuit included in the reference cell circuit executes the write operation one or more times, and causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell corresponding to the result of the comparison by the comparator.

### Claim 21

A method for setting a reference cell circuit including a first reference cell and a second reference cell each of which includes a variable resistance element which reversibly changes between a low resistance state and a high resistance state according to an application of an electric signal, the low resistance state having a resistance value within a first range, the high resistance state having a resistance value within a second range which has a lower limit value higher than an upper limit value of the first range, and the method comprising:
applying an electric signal one or more times to a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value further from a target resistance value according to each result of a comparison between a resistance value of the first reference cell and a resistance value of the second reference cell, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to the target resistance value, the target resistance value being a lower limit value or an upper limit value of a target state that is one of the low resistance state and the high resistance state, and the electric signal being for setting the reference cell to the target state; and
after the applying, electrically connecting, to an output terminal, one of the first reference cell and the second reference cell which has a resistance value closer to the target resistance value according to a result of a comparison between the resistance value of the first reference cell and the resistance value of the second reference cell.

### Claim 22

A method for controlling a variable resistance nonvolatile memory device including a plurality of memory cells, a first reference cell and a second reference cell, each of which includes a variable resistance element which reversibly changes between a low resistance state and a high resistance state according to an application of an electric signal, the low resistance state having a resistance value within a first range, the high resistance state having a resistance value within a second range which has a lower limit value higher than an upper limit value of the first range, the memory cells being arranged in rows and columns to form a memory cell array, the first reference cell and the reference cell forming a reference cell circuit, and the method comprising:
applying an electric signal one or more times to a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value further from a target resistance value according to each result of a comparison between a resistance value of the first reference cell and a resistance value of the second reference cell, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to the target resistance value, the target resistance value being a lower limit value or an upper limit value of a target state that is one of the low resistance state and the high resistance state, and the electric signal being for setting the reference cell to the target state;
after the applying, electrically connecting, to an output terminal, one of the first reference cell and the second reference cell which has a resistance value closer to the target resistance value according to a result of a comparison between the resistance value of the first reference cell and the resistance value of the second reference cell;
generating a reference level for determining a resistance state of each of the memory cells, with reference to a resistance value of a reference cell connected to an output terminal of the reference cell circuit; and
determining whether each memory cell is in the low resistance state or in the high resistance state by comparing a signal level obtained from the memory cell with the generated reference level.

### Claim 23

A method for controlling a variable resistance nonvolatile memory device including a plurality of memory cells, a first reference cell and a second reference cell, each of which includes a variable resistance element which reversibly changes between a low resistance state and a high resistance state according to an application of an electric signal, the low resistance state having a resistance value within a first range, the high resistance state having a resistance value within a second range which has a lower limit value higher than an upper limit value of the first range, the memory cells being arranged in rows and columns to form a memory cell array, the first reference cell and the reference cell forming a reference cell circuit, and the method comprising:
applying an electric signal one or more times to a reference cell that is one of the first reference cell and the second reference cell and that has a resistance value further from a target resistance value according to each result of a comparison between a resistance value of the first reference cell and a resistance value of the second reference cell, to make the resistance value of the first reference cell or the resistance value of the second reference cell close to the target resistance value, the target resistance value being a lower limit value or an upper limit value of a target state that is one of the low resistance state and the high resistance state, and the electric signal being for setting the reference cell to the target state;
after the applying, electrically connecting, to an output terminal, one of the first reference cell and the second reference cell which has a resistance value closer to the target resistance value according to a result of a comparison between the resistance value of the first reference cell and the resistance value of the second reference cell;
outputting a refresh command signal when a resistance value of a reference cell connected to an output terminal of the reference cell circuit becomes a predetermined value; and
performing a read operation and then a refresh operation on at least a part of the memory cells in the memory cell array when the refresh command signal is output, the read operation being for reading data from the part of the memory cells, and the refresh operation being for rewriting the read data to the part of the memory cells.

### Claim 24 (depends on 15)

The variable resistance nonvolatile memory device according to claim 15,
wherein, at a manufacturing process of the variable resistance nonvolatile memory device, the control circuit included in the reference cell circuit executes the write operation one or more times, and causes the output circuit to electrically connect, to the output terminal, one of the first reference cell and the second reference cell corresponding to the result of the comparison by the comparator.