# US 8,787,067 B2 · Semiconductor device and method of controlling semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,067 B2 - Document ID: US8787067B2 - Status: Granted - Kind: B2 - Application number: 13/359,449 - Filed: 2012-01-26 - Published: 2012-08-02 - Granted: 2014-07-22 - Earliest claimed: 2011-01-31 - Assignees: Renesas Electronics Corporation - Applicants: Motofumi Saitoh; Masayuki Terai - Inventors: Motofumi Saitoh; Masayuki Terai - Web page: https://patentgrep.com/patent/US8787067B2 ## CPC - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 13/003: {Cell access} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors} - H10N 70/20: Multistable switching devices, e.g. memristors - H10N 70/883: {Oxides or nitrides} - G11C 2013/0083: {Write to perform initialising, forming process, electro forming or conditioning} - G11C 2013/009: {Write using potential difference applied between cell electrodes} - G11C 2213/15: Current-voltage curve - G11C 2213/54: Structure including a tunneling barrier layer, the memory effect implying the modification of tunnel barrier conductivity - G11C 2213/56: Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way - G11C 2213/74: Array wherein each memory cell has more than one access device - G11C 2213/79: Array wherein the access device being a transistor - G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR ## Abstract Provided is a semiconductor device including: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a lower electrode contains a first metal material, an upper electrode containing a second metal material, and an insulating film containing oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the upper electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the lower electrode at the time of an operation of reading out the resistance value of the insulating film. ## Claims ### Claim 1 A semiconductor device comprising: a memory cell having a variable resistance device; and a control unit that controls a voltage applied to the memory cell, wherein the variable resistance device includes a first electrode containing a first metal material, a second electrode containing a second metal material, and an insulating film, provided between the first electrode and the second electrode, that contains a third metal material and oxygen, the first metal material has a normalized oxide formation energy higher than that of the second metal material, and the control unit applies a positive voltage to the second electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applies a positive voltage to the first electrode at the time of an operation of reading out the resistance value of the insulating film. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein when normalized oxide formation energies of the first metal material, the second metal material, and the third metal material are defined as ΔHf1, ΔHf2, and ΔHf3, respectively, relationships of ΔHf1≧ΔHf3/7+220 (kJ/mol) and ΔHf2≦ΔHf3/7+100 (kJ/mol) are satisfied. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the variable resistance device is a unipolar type. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the insulating film is formed of Ta2O5, a laminated film of Ta2O5 and TiO2, ZrO2, a laminated film of ZrO2 and Ta2O5, NiO, SrTiO3, SrRuO3, Al2O3, La2O3, HfO2, Y2O3 or V2O5. ### Claim 5 (depends on 4) The semiconductor device according to claim 4, wherein the insulating film is formed of Ta2O5, and when the normalized oxide formation energies of the first metal material and the second metal material are defined as ΔHf1 and ΔHf2, respectively, relationships of ΔHf1>280 (kJ/mol) and ΔHf2<160 (kJ/mol) are satisfied. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the first electrode is formed of W, Al, TiN, Ti, Ta, TaN, Hf, HfN, Zr, ZrN, or an alloy thereof. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the second electrode is formed of Ru, RuO2, Pt, Ir, Rh, Pd, Cu, or an alloy thereof. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein the positive voltage applied to the first electrode at the time of the operation of reading out the resistance value of the insulating film is 0.8 V or higher. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, further comprising a first interfacial layer, provided between the first electrode and the insulating film, wherein a stoichimetric composition of the first interfacial layer is expressed by MxOy (M: metal element), and the interfacial layer has a composition ratio of oxygen to a metal element M which is smaller than y/x. ### Claim 10 (depends on 9) The semiconductor device according to claim 9, wherein the first interfacial layer has Ta2O5 as a stoichiometric composition. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, further comprising a second interfacial layer provided between the first electrode and the insulating film, formed of a metal oxide of which an electronic density of states at a conduction band minimum is equal to or smaller than an electronic density of states at a valence band maximum. ### Claim 12 (depends on 11) The semiconductor device according to claim 11, wherein the second interfacial layer is a layer formed of MgO, CaO, Al2O3, Ga2O3, or SiO2, or a layer including at least one of MgO, CaO, Al2O3, Ga2O3, and SiO2. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, further comprising a third interfacial layer, provided between the first electrode and the insulating film, which is formed of an oxide of a metal material having a valence lower than that of the third metal material constituting the insulating film. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the third metal material is Al, Y or La, and the third interfacial layer is a layer formed of MgO or CaO, or a layer including at least one of MgO and CaO. ### Claim 15 (depends on 13) The semiconductor device according to claim 13, wherein the third metal material is Ti, Zr or Hf, and the third interfacial layer is a layer formed of MgO, CaO, Al2O3, Y2O3 or La2O3, or a layer including at least one of MgO, CaO, Al2O3, Y2O3 and La2O3. ### Claim 16 (depends on 13) The semiconductor device according to claim 13, wherein the third metal material is V or Ta, and the third interfacial layer is a layer formed of MgO, CaO, Al2O3, Y2O3, La2O3, TiO2, ZrO2, or HfO2, or a layer including at least one of MgO, CaO, Al2O3, Y2O3, La2O3, TiO2, ZrO2, and HfO2. ### Claim 17 (depends on 1) The semiconductor device according to claim 1, further comprising a fourth interfacial layer, provided between the first electrode and the insulating film, which has an impurity functioning as a donor. ### Claim 18 (depends on 1) The semiconductor device according to claim 1, wherein the memory cell has a selection transistor, and the control unit applies a positive voltage to the first electrode side, and then stops the application of a positive voltage to the first electrode side, and applies a positive voltage to the selection transistor, at the time of the operation of reading out the resistance value of the insulating film. ### Claim 19 (depends on 18) The semiconductor device according to claim 18, wherein the first electrode is connected to the selection transistor. ### Claim 20 (depends on 1) The semiconductor device according to claim 1, further comprising an interconnect provided on the memory cell, wherein the memory cell has a selection transistor, and one of the first electrode and the second electrode is connected to the interconnect, and the other one is connected to a source/drain region of the selection transistor. ### Claim 21 (depends on 20) The semiconductor device according to claim 20, wherein the other one of the first electrode and the second electrode is constituted by a first contact that connects the insulating film and the source/drain region. ### Claim 22 (depends on 20) The semiconductor device according to claim 20, further comprising a silicide layer formed in a surface of the source/drain region, wherein the other one of the first electrode and the second electrode is formed of the silicide layer. ### Claim 23 (depends on 20) The semiconductor device according to claim 20, further comprising the plurality of memory cells arranged in an array. ### Claim 24 (depends on 23) The semiconductor device according to claim 23, wherein two adjacent memory cells are configured such that one of the source/drain regions which is not connected to the variable resistance device is formed integrally therewith, and the source/drain region integrally formed is connected to a bit line through one bit contact. ### Claim 25 (depends on 23) The semiconductor device according to claim 23, further comprising a device isolation electrode located between the selection transistor included in one memory cell and the selection transistor included in another memory cell adjacent to the one memory cell. ### Claim 26 (depends on 23) The semiconductor device according to claim 23, wherein the two adjacent memory cells connected to the same bit line are configured such that the one of the first electrode and the second electrode is formed integrally therewith, the other is separated therefrom, and the one of the first electrode and the second electrode which is formed integrally therewith is connected to a plate line through one plate contact. ### Claim 27 (depends on 23) The semiconductor device according to claim 23, wherein the two adjacent memory cells connected to bit lines different from each other are configured such that the one of the first electrode and the second electrode is formed integrally therewith, the other is separated therefrom, and the one of the first electrode and the second electrode which is formed integrally therewith is connected to a plate line through one plate contact. ### Claim 28 (depends on 23) The semiconductor device according to claim 23, wherein the plurality of memory cells which is connected to bit lines different from each other and is arranged in one direction is configured such that the one of the first electrode and the second electrode is formed integrally therewith, and the other is separated therefrom. ### Claim 29 (depends on 20) The semiconductor device according to claim 20, wherein the one of the first electrode and the second electrode is constituted by a second contact that connects the interconnect and the insulating film. ### Claim 30 (depends on 20) The semiconductor device according to claim 20, wherein the one of the first electrode and the second electrode is constituted by the interconnect. ### Claim 31 A method of controlling a semiconductor device including a first electrode containing a first metal material, a second electrode containing a second metal material, and an insulating film, provided between the first electrode and the second electrode, that contains a third metal material and oxygen, the first metal material having a normalized oxide formation energy higher than that of the second metal material, the method comprising: applying a positive voltage to the second electrode at the time of an operation of increasing a resistance value of the insulating film and an operation of decreasing the resistance value thereof, and applying a positive voltage to the first electrode at the time of an operation of reading out the resistance value of the insulating film.