# US 8,787,061 B2 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,061 B2 - Document ID: US8787061B2 - Status: Granted - Kind: B2 - Application number: 13/524,750 - Filed: 2012-06-15 - Published: 2012-12-20 - Granted: 2014-07-22 - Earliest claimed: 2011-06-17 - Assignees: Kabushiki Kaisha Toshiba - Applicants: Fumihiro Kono - Inventors: Fumihiro Kono - Web page: https://patentgrep.com/patent/US8787061B2 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/26: Sensing or reading circuits; Data output circuits - H10B 41/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 43/30: characterised by the memory core region - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/635: {Through-vias} - H10W 70/65: Shapes or dispositions of interconnections - G11C 2213/71: Three dimensional array - H10B 43/20: characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract According to an embodiment, a semiconductor memory device comprises: a semiconductor substrate; a memory cell array configured having a plurality of memory units, each of the memory units including a plurality of memory cells connected in series, the plurality of memory cells being stacked, the plurality of memory units involving a first memory unit and a second memory unit; and a plurality of bit lines connected to ends of each of the memory units in the memory cell array. The first memory unit and the second memory unit are arranged in a staggered manner by the first memory unit being displaced in a row direction with respect to the second memory unit by an amount less than an arrangement pitch in a row direction of the first memory unit or the second memory unit. ## Claims ### Claim 1 A semiconductor memory device, comprising: a semiconductor substrate; memory units including memory cells that are stacked above the semiconductor substrate, the memory units including a first memory unit, a second memory unit, and a third memory unit, the second memory unit being adjacent to the first memory unit in a first direction, the third memory unit being adj acent to the first memory unit in a second direction crossing the first direction, the first memory unit including a first memory cell, the second memory unit including a second memory cell, the third memory unit including a third memory cell, a gate of the first memory cell being electrically connected to a gate of the second memory cell; and bit lines disposed above the memory units, the bit lines extending in a third direction, the bit lines including a first bit line and a second bit line, the second bit line being adjacent to the first bit line in the first direction, the third direction being different from both the first direction and the second direction, and the third direction being parallel to the semiconductor substrate, wherein a first pitch is larger than a second pitch, the first pitch being a distance between the first memory unit and the second memory unit, the second pitch being a distance between the first bit line and the second bit line. ### Claim 2 (depends on 1) The semiconductor memory device according to claim 1, wherein the second pitch is 1/n times the first pitch (where n is an integer of 2 or more). ### Claim 3 (depends on 1) The semiconductor memory device according to claim 1, wherein one of the memory units comprises: a semiconductor body extending in a direction perpendicular to the semiconductor substrate; a charge storage layer surrounding the semiconductor body; and a word line surrounding the charge storage layer. ### Claim 4 (depends on 1) The semiconductor memory device according to claim 1, wherein one of the memory units comprises a U-shaped semiconductor body including two semiconductor pillars and a first portion, one end of the first portion being connected to one of the semiconductor pillars, the other end of the first portion being connected to another one of the semiconductor pillars, and a sense amplifiers circuit electrically connected to the bit lines, the sense amplifiers circuit being disposed below the memory units. ### Claim 5 (depends on 3) The semiconductor memory device according to claim 3, wherein a width of the bit lines in the first direction is smaller than a width of the semiconductor body. ### Claim 6 (depends on 1) The semiconductor memory device according to claim 1, further comprising: a first contact electrically connected to one end of the first memory unit; and a second contact electrically connected to one end of the second memory unit, wherein a width of the first memory unit is larger than a width of the first contact and a width of the second memory unit is larger than a width of the second contact. ### Claim 7 A semiconductor memory device, comprising: a semiconductor substrate; memory units including a first memory unit, a second memory unit, and a third memory unit, the second memory unit being adjacent to the first memory unit in a first direction, the third memory unit being adjacent to the first memory unit in a second direction crossing the first direction, the first memory unit including a first memory cell, the second memory unit including a second memory cell, the third memory unit including a third memory cell, a gate of the first memory cell being electrically connected to a gate of the second memory cell; and bit lines disposed above the memory units, the bit lines extending in a third direction, the third direction being different from both the first direction and the second direction, the third direction being parallel to the semiconductor substrate, wherein a distance between the first memory unit and the third memory unit in the third direction is smaller than a distance between the first memory unit and the second memory unit in the first direction. ### Claim 8 (depends on 7) The semiconductor memory device according to claim 7, wherein the bit lines are arranged in the first direction with a second pitch that is 1/n times a first pitch (where n is an integer of 2 or more), the first pitch being a distance between the first memory unit and the second memory unit, the second pitch being a distance between a first bit line and a second bit line. ### Claim 9 (depends on 7) The semiconductor memory device according to claim 7, wherein one of the memory units comprises: a semiconductor body extending in a direction perpendicular to the semiconductor substrate; a charge storage layer surrounding the semiconductor body; a word line surrounding the charge storage layer. ### Claim 10 (depends on 7) The semiconductor memory device according to claim 7, wherein one of the memory units comprises a U-shaped semiconductor body including two semiconductor pillars and a first portion, one end of the first portion being connected to one of the semiconductor pillars, the other end of the first portion being connected to another one of the semiconductor pillars, and sense amplifiers circuit electrically connected to the bit lines, the sense amplifiers circuit being disposed below the memory units. ### Claim 11 (depends on 9) The semiconductor memory device according to claim 9, wherein a width of the bit lines in the first direction is smaller than a width of the semiconductor body. ### Claim 12 (depends on 7) The semiconductor memory device according to claim 7, comprising: a first contact electrically connected to one end of the first memory unit; and a second contact electrically connected to one end of the second memory unit, wherein a width of the first memory unit is larger than a width of the first contact and a width of the second memory unit is larger than a width of the second contact. ### Claim 13 A semiconductor memory device, comprising: a semiconductor substrate; memory units including a first memory unit, a second memory unit, and a third memory unit, the second memory unit being adjacent to the first memory unit in a first direction, the third memory unit being adjacent to the first memory unit in a second direction crossing the first direction, the first memory unit including a first memory cell, the second memory unit including a second memory cell, the third memory unit including a third memory cell, and a gate of the first memory cell being electrically connected to a gate of the second memory cell; and bit lines disposed above the memory units, the bit lines extending in a third direction, the third direction being different from both the first direction and the second direction, the third direction being parallel to the semiconductor substrate, wherein the memory units comprise: a semiconductor body extending in a direction perpendicular to the semiconductor substrate; a charge storage layer surrounding the semiconductor body; and a word line surrounding the charge storage layer, and a length of the word line in the third direction is smaller than a sum of two closet distances in the third direction from sides of the semiconductor bodies to both ends of the word line, two diameter's width of the semiconductor body, and a spacing between the semiconductor body of the first memory cell and the semiconductor body of the third memory cell. ### Claim 14 (depends on 13) The semiconductor memory device according to claim 13, wherein the bit lines include a first bit line and a second bit line, the second bit line being adjacent to the first bit line in the first direction. ### Claim 15 (depends on 14) The semiconductor memory device according to claim 14, wherein the bit lines are arranged in the first direction with a second pitch that is 1/n times a first pitch (where n is an integer of 2 or more), the first pitch being a distance between the first memory unit and the second memory unit, the second pitch being a distance between the first bit line and the second bit line. ### Claim 16 (depends on 13) The semiconductor memory device according to claim 13, wherein one of the memory units comprises a U-shaped semiconductor body including two semiconductor pillars and a first portion, one end of the first portion being connected to one of the semiconductor pillars, the other end of the first portion being connected to another one of the semiconductor pillars, and a sense amplifier circuit electrically connected to the bit lines, the sense amplifiers circuit being disposed below the memory units. ### Claim 17 (depends on 13) The semiconductor memory device according to claim 13, wherein a width of the bit lines in the first direction is smaller than a diameter of the semiconductor body. ### Claim 18 (depends on 13) The semiconductor memory device according to claim 13, further comprising: a first contact electrically connected to one end of the first memory unit; and a second contact electrically connected to one end of the second memory unit, wherein a width of the first memory unit is larger than a width of the first contact and a width of the second memory unit is larger than a width of the second contact.