# US 8,787,059 B1 · Cascaded content addressable memory array having multiple row segment activation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,787,059 B1 - Document ID: US8787059B1 - Status: Granted - Kind: B1 - Application number: 13/311,301 - Filed: 2011-12-05 - Granted: 2014-07-22 - Earliest claimed: 2011-12-05 - Assignees: NetLogic Microsystems, Inc. - Applicants: Vinay Iyengar - Inventors: Vinay Iyengar - Web page: https://patentgrep.com/patent/US8787059B1 ## CPC - G11C 15/04: using semiconductor elements - G06F 16/90339: {by using parallel associative memories or content-addressable memories} - G11C 15/00: Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores - G11C 7/1048: {Data bus control circuits, e.g. precharging, presetting, equalising} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A content addressable memory (CAM) device has an array including a plurality of CAM rows that are partitioned into row segments, wherein a respective row includes a first row segment including a number of first CAM cells coupled to a first match line segment, a second row segment including a number of second CAM cells coupled to a second match line segment, and a circuit to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. Power consumption can be reduced during compare operations in which the first row segment of another row that stores the same data as the first row segment of the respective row is not enabled. ## Claims ### Claim 1 A content addressable memory (CAM) device having an array including a plurality of rows, wherein a respective row of the plurality of rows comprises: a first row segment including a number of first CAM cells coupled to a first match line segment; and a first circuit configured to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row. ### Claim 2 (depends on 1) The CAM device of claim 1, wherein: the first circuit is further configured to disable the first row segment of the respective row during a compare operation if the value indicates that data stored in the first row segment of the respective row is the same as data stored in the first row segment of the other row. ### Claim 3 (depends on 1) The CAM device of claim 1, wherein: the first circuit is further configured to enable the first row segment of the respective row during a compare operation if the value indicates that data stored in the first row segment of the respective row is not the same as data stored in the first row segment of the other row. ### Claim 4 (depends on 1) The CAM device of claim 1, further comprising: a second row segment including a number of second CAM cells coupled to a second match line segment; and a second circuit configured to selectively pre-charge the second match line segment of the respective row in response to match conditions in the first row segment of the other row if the value indicates that data stored in the first row segment of the respective row is the same as data stored in the first row segment of the other row. ### Claim 5 (depends on 4) The CAM device of claim 4, wherein the second circuit is further configured to selectively pre-charge the second match line segment of the other row during a compare operation. ### Claim 6 (depends on 4) The CAM device of claim 4, further comprising: an interconnect circuit having first inputs coupled to the first match line segments, second inputs to receive the values, and outputs coupled to the second match line segments. ### Claim 7 (depends on 6) The CAM device of claim 6, wherein the interconnect circuit is configured to selectively enable the second row segments in response to a combination of match conditions in the first row segments and the values. ### Claim 8 (depends on 6) The CAM device of claim 6, wherein the interconnect circuit is configured to selectively enable the second row segments of a group of rows in response to match conditions in the first row segment of a designated row of the group of rows if the value indicates that the first row segments of the group of rows store the same data. ### Claim 9 (depends on 6) The CAM device of claim 6, wherein the interconnect circuit includes a plurality of multiplexers, wherein a respective multiplexer of the plurality of multiplexers comprises: a first input coupled to the first match line segment of the respective row; a second input coupled to the first match line segment of the other row; an output coupled to the second match line segment of the respective row; and a control input to receive the value for the respective row. ### Claim 10 (depends on 1) The CAM device of claim 1, further comprising: a processor, having an input to receive data entries for the array and having first outputs coupled to the first circuits, configured to generate the values in response to a comparison between the data entries to be stored in the array. ### Claim 11 (depends on 10) The CAM device of claim 10, wherein the processor is further configured to store the data entries in the array in an order so that groups of data entries having common prefixes are stored in corresponding groups of adjacent rows of the array. ### Claim 12 (depends on 10) The CAM device of claim 10, wherein the processor further includes a second output coupled to an interconnect circuit spanning across all rows of the array. ### Claim 13 (depends on 10) The CAM device of claim 10, wherein the processor comprises a parity check circuit. ### Claim 14 A content addressable memory (CAM) array having a plurality of rows, wherein a respective row of the plurality of rows comprises: a first row segment including a number of first CAM cells coupled to a first match line segment; a first circuit configured to selectively pre-charge the first match line segment in response to a value indicating whether data stored in the first row segment of the respective row is the same as data stored in the first row segment of another row; a second row segment including a number of second CAM cells coupled to a second match line segment; and a second circuit configured to selectively pre-charge the second match line segment of the respective row in response to a combination of match conditions in the first row segments and the value. ### Claim 15 (depends on 14) The CAM array of claim 14, wherein: if the value indicates that data stored in the first row segment of the respective row is the same as data stored in the first row segment of the other row, then the first circuit is configured to not pre-charge the first match line segment of the respective row. ### Claim 16 (depends on 14) The CAM array of claim 14, wherein: if the value indicates that data stored in the first row segment of the respective row is not the same as data stored in the first row segment of the other row, then the first circuit is configured to pre-charge the first match line segment of the respective row. ### Claim 17 (depends on 14) The CAM array of claim 14, wherein the second circuits associated with the plurality of rows together comprise an interconnect circuit having first inputs coupled to the first match line segments of the rows, second inputs to receive the values, and outputs coupled to the second match line segments of the rows. ### Claim 18 (depends on 17) The CAM array of claim 17, wherein the interconnect circuit is configured to selectively enable the second row segments of a group of rows in response to a combination of the value and match conditions in the first row segment of a designated row of the group of rows. ### Claim 19 (depends on 17) The CAM array of claim 17, wherein the interconnect circuit is configured to selectively enable the second row segments of a group of rows in response to match conditions in the first row segment of a designated row of the group of rows if the value indicates that the first row segments of the group of rows store the same data. ### Claim 20 (depends on 17) The CAM array of claim 17, wherein the interconnect circuit is configured to selectively enable the second row segment of a particular row only in response to match conditions in the first row segment of the particular row if the value indicates that the first row segments of the plurality of rows do not store the same data. ### Claim 21 (depends on 17) The CAM array of claim 17, wherein the interconnect circuit includes a plurality of multiplexers, wherein a respective multiplexer of the plurality of multiplexers comprises: a first input coupled to the first match line segment of the respective row; a second input coupled to the first match line segment of another row; an output coupled to the second match line segment of the respective row; and a control input to receive the value for the respective row. ### Claim 22 (depends on 14) The CAM array of claim 14, further comprising: a processor, having an input to receive data entries for the CAM array, having first outputs coupled to the first circuits, and having second outputs coupled to the second circuits, configured to generate the values in response to a comparison between the data entries to be stored in the CAM array. ### Claim 23 (depends on 22) The CAM array of claim 22, wherein the processor is further configured to store the data entries in the array in an order so that groups of data entries having common prefixes are stored in corresponding groups of adjacent rows of the CAM array. ### Claim 24 (depends on 22) The CAM array of claim 22, wherein the processor comprises a parity check circuit. ### Claim 25 A content addressable memory (CAM) device, comprising: a CAM array having a plurality of rows, wherein each row includes a first segment having a number of first CAM cells coupled to a first match line segment and includes a second segment having a number of second CAM cells coupled to a second match line segment; and an interconnect circuit having first inputs coupled to the first match line segments, second inputs to receive a number of values indicating whether the first row segments of a group of rows store the same data, and outputs coupled to the second match line segments. ### Claim 26 (depends on 25) The CAM device of claim 25, wherein the interconnect circuit is configured to selectively transmit match results from the first segment of a designated row of a respective group to the second segments of each of the rows in the respective group in response to a corresponding one of the values. ### Claim 27 (depends on 25) The CAM device of claim 25, wherein a respective row of the plurality of rows comprises: a circuit having an input to receive a corresponding one of the values and having an output coupled to the first match line segment of the respective row. ### Claim 28 (depends on 27) The CAM device of claim 27, wherein the circuit is configured to selectively pre-charge the first match line segment of the respective row in response to the corresponding one of the values. ### Claim 29 (depends on 28) The CAM device of claim 28, wherein the circuit is further configured to disable the first segment of the respective row in response to the corresponding one of the values indicating that data stored in the first segment of the respective row is the same as data stored in the first row segment of another row. ### Claim 30 (depends on 25) The CAM device of claim 25, further comprising: a processor configured to order a plurality of data entries for the CAM array, wherein the data entries within a respective group share a common prefix. ### Claim 31 (depends on 30) The CAM device of claim 30, wherein the processor comprises a parity check circuit.