# US 8,786,794 B2 · Semiconductor device

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- Number: US 8,786,794 B2
- Document ID: US8786794B2
- Status: Granted
- Kind: B2
- Application number: 13/967,645
- Filed: 2013-08-15
- Published: 2013-12-12
- Granted: 2014-07-22
- Earliest claimed: 2004-09-15
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Yoshinari Higaki; Masayuki Sakakura; Shunpei Yamazaki
- Web page: https://patentgrep.com/patent/US8786794B2

## CPC

- H10D 30/6732: {Bottom-gate only TFTs}
- H10D 30/67: Thin-film transistors [TFT] {(Stacked nanowire, nanosheet or nanoribbon FETs H10D30/501)}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/6737: {characterised by the electrode materials}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6743: {Silicon}
- H10D 30/6746: {Amorphous silicon}
- H10D 86/00: Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

It is an object of the present invention to connect a wiring, an electrode, or the like formed with two incompatible films (an ITO film and an aluminum film) without increasing the cross-sectional area of the wiring and to achieve lower power consumption even when the screen size becomes larger. The present invention provides a two-layer structure including an upper layer and a lower layer having a larger width than the upper layer. A first conductive layer is formed with Ti or Mo, and a second conductive layer is formed with aluminum (pure aluminum) having low electric resistance over the first conductive layer. A part of the lower layer projected from the end section of the upper layer is bonded with ITO.

## Claims

### Claim 1

A semiconductor device comprising:
a gate electrode over a substrate;
a gate insulating layer over the gate electrode;
a semiconductor layer over the gate insulating layer; and
a source electrode and a drain electrode, over the semiconductor layer,
wherein one of the source electrode and the drain electrode is electrically connected to the semiconductor layer, and has a first electrode layer and a second electrode layer,
wherein the second electrode layer is formed on the first electrode layer,
wherein the first electrode layer comprises titanium,
wherein the second electrode layer comprises aluminum,
wherein a first width of the first electrode layer is larger than a second width of the second electrode layer,
wherein an upper surface of the second electrode layer is in contact with an insulating layer,
wherein the first electrode layer is in contact with a pixel electrode,
wherein the semiconductor layer comprises an amorphous silicon, and
wherein the pixel electrode comprises an ITO.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein the second electrode layer is in contact with the pixel electrode.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, further comprising:
a second insulating layer between the semiconductor layer and the one of the source electrode and the drain electrode.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein the gate electrode comprises tantalum nitride and tungsten.

### Claim 5

A semiconductor device comprising:
a gate electrode over a substrate;
a gate insulating layer over the gate electrode;
a semiconductor layer over the gate insulating layer;
a source electrode and a drain electrode, over the semiconductor layer;
a pixel electrode electrically connected to one of the source electrode and the drain electrode;
an orientation film over the pixel electrode; and
a liquid crystal layer over the orientation film,
wherein one of the source electrode and the drain electrode is electrically connected to the semiconductor layer, and has a first electrode layer and a second electrode layer,
wherein the second electrode layer is formed on the first electrode layer,
wherein the first electrode layer comprises titanium,
wherein the second electrode layer comprises aluminum,
wherein a first width of the first electrode layer is larger than a second width of the second electrode layer,
wherein an upper surface of the second electrode layer is in contact with an insulating layer,
wherein the first electrode layer is in contact with the pixel electrode,
wherein the semiconductor layer comprises an amorphous silicon, and
wherein the pixel electrode comprises an ITO.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5,
wherein the second electrode layer is in contact with the pixel electrode.

### Claim 7 (depends on 5)

The semiconductor device according to claim 5, further comprising:
a second insulating layer between the semiconductor layer and the one of the source electrode and the drain electrode.

### Claim 8 (depends on 5)

The semiconductor device according to claim 5,
wherein the gate electrode comprises tantalum nitride and tungsten.

### Claim 9

A semiconductor device comprising:
a gate electrode over a substrate;
a gate insulating layer over the gate electrode;
a semiconductor layer over the gate insulating layer;
a source electrode and a drain electrode, over the semiconductor layer;
a pixel electrode electrically connected to one of the source electrode and the drain electrode;
an orientation film over the pixel electrode; and
a liquid crystal layer over the orientation film,
wherein one of the source electrode and the drain electrode is electrically connected to the semiconductor layer, and has a first electrode layer and a second electrode layer,
wherein the second electrode layer is formed on the first electrode layer,
wherein the first electrode layer comprises titanium,
wherein the second electrode layer comprises aluminum,
wherein a first width of the first electrode layer is larger than a second width of the second electrode layer,
wherein an upper surface of the second electrode layer is in contact with an insulating layer,
wherein the first electrode layer is in contact with the pixel electrode,
wherein the semiconductor layer comprises an amorphous silicon,
wherein the pixel electrode comprises an ITO, and
wherein the gate electrode, the semiconductor layer, the source electrode and the drain electrode are provided in a pixel region.

### Claim 10 (depends on 9)

The semiconductor device according to claim 9,
wherein the second electrode layer is in contact with the pixel electrode.

### Claim 11 (depends on 9)

The semiconductor device according to claim 9, further comprising:
a second insulating layer between the semiconductor layer and the one of the source electrode and the drain electrode.

### Claim 12 (depends on 9)

The semiconductor device according to claim 9,
wherein the gate electrode comprises tantalum nitride and tungsten.