# US 8,786,792 B2 · Mother substrate for liquid crystal display device and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,792 B2 - Document ID: US8786792B2 - Status: Granted - Kind: B2 - Application number: 12/654,069 - Filed: 2009-12-09 - Published: 2010-07-01 - Granted: 2014-07-22 - Earliest claimed: 2008-12-26 - Assignees: LG Display Co., Ltd. - Applicants: Jeong-yeop Lee; Jae-myung Seok; Jae-woo Jung; Young-seok Choi; Hyock-jae Shin - Inventors: Jeong-yeop Lee; Jae-myung Seok; Jae-woo Jung; Young-seok Choi; Hyock-jae Shin - Web page: https://patentgrep.com/patent/US8786792B2 ## CPC - G02F 1/133351: {Manufacturing of individual cells out of a plurality of cells, e.g. by dicing} - G02F 1/136204: {Arrangements to prevent high voltage or static electricity failures} - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract A mother substrate for a liquid crystal display device includes: a substrate; a plurality of unit array patterns on the substrate, each of the plurality of unit array patterns including a gate line, a data line crossing the gate line, a thin film transistor connected to the gate line and the data line and a pixel electrode connected to the thin film transistor; a first electrostatic discharge pattern surrounding the plurality of unit array patterns; a second electrostatic discharge pattern connected to the gate line and crossing the first electrostatic discharge pattern; and a third electrostatic discharge pattern connected to the data line and crossing the first electrostatic discharge pattern, the third electrostatic discharge pattern contacting the second electrostatic discharge pattern. ## Claims ### Claim 1 A mother substrate for a liquid crystal display device, comprising: a substrate; a plurality of unit array patterns on the substrate, each of the plurality of unit array patterns including a gate line, a data line crossing the gate line, a thin film transistor connected to the gate line and the data line and a pixel electrode connected to the thin film transistor; a first electrostatic discharge pattern surrounding the plurality of unit array patterns; a second electrostatic discharge pattern connected to the gate line and crossing the first electrostatic discharge pattern; and a third electrostatic discharge pattern connected to the data line and crossing the first electrostatic discharge pattern, the third electrostatic discharge pattern electrically connected to the second electrostatic discharge pattern. ### Claim 2 (depends on 1) The mother substrate according to claim 1, wherein the first electrostatic discharge pattern has a rectangular closed loop shape. ### Claim 3 (depends on 1) The mother substrate according to claim 1, wherein the first and second electrostatic discharge patterns have the same layer and the same material as the gate line. ### Claim 4 (depends on 1) The mother substrate according to claim 1, wherein the third electrostatic discharge pattern has the same layer and the same material as the data line. ### Claim 5 (depends on 1) The mother substrate according to claim 1, wherein the substrate includes a central portion and an edge portion surrounding the central portion, wherein the plurality of unit array patterns are disposed in the central portion and the first electrostatic discharge pattern is disposed at a boundary portion between the central portion and the edge portion, and wherein the second and third electrostatic discharge patterns extend from the central portion to the edge portion. ### Claim 6 (depends on 5) The mother substrate according to claim 5, further comprising a shortage pattern connecting the second and third electrostatic discharge patterns at the edge portion, wherein the shortage pattern comprises: a first slit pattern connected to the second electrostatic discharge pattern and having a width greater than the second electrostatic discharge pattern; and a second slit pattern connected to the third electrostatic discharge pattern and having a width greater than the third electrostatic discharge pattern, the second slit pattern contacting the first slit pattern. ### Claim 7 (depends on 6) The mother substrate according to claim 6, wherein the first slit pattern includes openings and bar patterns along a first direction and the second slit pattern includes openings and bar patterns along a second direction perpendicular to the first direction. ### Claim 8 (depends on 6) The mother substrate according to claim 6, further comprising a gate insulating layer between the gate line and the data line, wherein the first slit pattern has the same layer and the same material as the gate line and the second slit pattern has the same layer and the same material as the data line, and wherein the first and second slit patterns directly contact each other without the gate insulating layer interposed therebetween. ### Claim 9 (depends on 1) The mother substrate according to claim 1, wherein the first electrostatic discharge pattern has a first slit part at a crossing portion of the first and third electrostatic discharge patterns and the third electrostatic discharge pattern has a second slit part at the crossing portion of the first and third electrostatic discharge patterns, wherein the first slit part includes first slant openings and first slant bar patterns, wherein the second slit part includes second slant openings and second slant bar patterns, and wherein a slant direction of the first slant openings and the first slant bar patterns is opposite to a slant direction of the second slant openings and the second slant bar patterns. ### Claim 10 A method of fabricating a mother substrate for a liquid crystal display device, comprising: forming a plurality of unit array patterns on a substrate, each of the plurality of unit array patterns including a gate line, a data line crossing the gate line, a thin film transistor connected to the gate line and the data line and a pixel electrode connected to the thin film transistor; forming a first electrostatic discharge pattern surrounding the plurality of unit array patterns; forming a second electrostatic discharge pattern connected to the gate line and crossing the first electrostatic discharge pattern; and forming a third electrostatic discharge pattern connected to the data line and crossing the first electrostatic discharge pattern, the third electrostatic discharge pattern electrically connected to the second electrostatic discharge pattern. ### Claim 11 (depends on 10) The method according to claim 10, wherein the substrate includes a central portion and an edge portions surrounding the central portion, wherein the plurality of unit array patterns are disposed in the central portion and the first electrostatic discharge pattern is disposed at a boundary portion between the central portion and the edge portion, and wherein the second and third electrostatic discharge patterns extend from the central portion to the edge portion. ### Claim 12 (depends on 11) The method according to claim 11, further comprising: forming a first slit pattern connected to the second electrostatic discharge pattern and having a width greater than the second electrostatic discharge pattern; and forming a second slit pattern connected to the third electrostatic discharge pattern and having a width greater than the third electrostatic discharge pattern, the second slit pattern contacting the first slit pattern, wherein the first and second slit patterns constitute a shortage pattern at the edge portion. ### Claim 13 (depends on 12) The method according to claim 12, further comprising forming a gate insulating layer on the gate line, the first electrostatic discharge pattern and the second electrostatic discharge pattern, wherein the first slit pattern is shielded from the gate insulating layer. ### Claim 14 A method of fabricating a liquid crystal display device, comprising: forming a plurality of unit array patterns on a first mother substrate, each of the plurality of unit array patterns including a gate line, a data line crossing the gate line, a thin film transistor connected to the gate line and the data line and a pixel electrode connected to the thin film transistor; forming a first electrostatic discharge pattern surrounding the plurality of unit array patterns; forming a second electrostatic discharge pattern connected to the gate line and crossing the first electrostatic discharge pattern; forming a third electrostatic discharge pattern connected to the data line and crossing the first electrostatic discharge pattern, the third electrostatic discharge pattern electrically connected to the second electrostatic discharge pattern; forming a plurality of unit color filter patterns on a second mother substrate, each of the plurality of unit color filter patterns including a black matrix, a color filter layer on the black matrix, a common electrode on the color filter layer; attaching the first and second mother substrates such that the pixel electrode faces the common electrode; cutting the first and second mother substrates along a substrate cutting line such that the first, second and third electrostatic discharge patterns are removed; and forming a liquid crystal layer between the pixel electrode and the common electrode.