# US 8,786,745 B2 · Solid-state image pickup device

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- Number: US 8,786,745 B2
- Document ID: US8786745B2
- Status: Granted
- Kind: B2
- Application number: 13/577,162
- Filed: 2011-01-28
- Published: 2013-02-21
- Granted: 2014-07-22
- Earliest claimed: 2010-02-05
- Assignees: National University Corporation Shizuoka University
- Applicants: Shoji Kawahito; Keita Yasutomi
- Inventors: Shoji Kawahito; Keita Yasutomi
- Web page: https://patentgrep.com/patent/US8786745B2

## CPC

- H04N 25/771: comprising storage means other than floating diffusion
- H04N 25/589: with different integration times, e.g. short and long exposures
- H04N 25/59: by controlling the amount of charge storable in the pixel, e.g. modification of the charge conversion ratio of the floating node capacitance
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION

## Abstract

In a pixel 11, a floating semiconductor region FD accumulates a charge from a photoelectric transducer PD. A first charge transfer path CTP1 extends from the photoelectric transducer PD to the floating semiconductor region FD through the storage diode SD. A second charge transfer path CTP2 extends from the photoelectric transducer PD to the floating semiconductor region. An output unit AMP provides a signal corresponding to a potential in the floating semiconductor region FD. The first charge transfer path CTP includes a first shutter switch TR(GS1) for controlling a transfer of the charge from the photoelectric transducer PD, the storage diode SD for accumulating the charge from the photoelectric transducer PD, and a transfer switch TR(TF1) for controlling a transfer of the charge from the storage diode SD to the floating semiconductor region PD, while the second charge transfer path CTP includes a shutter switch TR(GS2) for controlling a transfer of the charge from the photoelectric transducer PD.

## Claims

### Claim 1

A solid-state image pickup device comprising:
a pixel array including a plurality of pixels arranged in an array;
a control circuit for generating first, second, and third control signals for controlling the pixel;
a readout circuit for reading the first and second pixel signals from the pixel array in one frame; and
a signal processing unit for processing signals from the readout circuit;
wherein each pixel includes:
a photoelectric transducer for generating an electric signal from light received thereby;
a floating semiconductor region for accumulating a charge from the photoelectric transducer;
a first charge transfer path extending from the photoelectric transducer to the floating semiconductor region;
a second charge transfer path extending from the photoelectric transducer to the floating semiconductor region; and
an output unit for providing a signal corresponding to a potential in the floating semiconductor region;
wherein one of the first and second charge transfer paths includes a first shutter switch for controlling a transfer of the charge from the photoelectric transducer in response to the first control signal, a first storage diode for accumulating the charge from the photoelectric transducer, and a first transfer switch for controlling a transfer of the charge from the first storage diode to the floating semiconductor region in response to the second control signal;
wherein the other of the first and second charge transfer paths includes a second shutter switch for controlling a transfer of the charge from the photoelectric transducer to the floating semiconductor region through no charge storage unit in response to the third control signal;
wherein the first pixel signal corresponds to a first transfer charge transferred to the floating semiconductor region through the first charge transfer path;
wherein the second pixel signal corresponds to a second transfer charge transferred to the floating semiconductor region through the second charge transfer path;
wherein a first accumulation period for accumulating the charge transferred through the one charge transfer path is longer than a second accumulation period for accumulating the charge transferred through the other charge transfer path;
wherein the signal processing unit includes a signal synthesis unit for synthesizing a synthetic image signal from the first and second pixel signals;
wherein the synthetic image signal has a dynamic range wider than that of each of the first and second image signals;
wherein the pixel includes a reset switch for resetting the floating semiconductor region;
wherein the control circuit generates a reset signal for controlling the reset switch;
wherein the first pixel signal includes a first signal level corresponding to the first transfer charge and a first reset level corresponding to a potential of the floating semiconductor region reset by the reset switch;
wherein the second pixel signal includes a second signal level corresponding to the second transfer charge and a second reset level corresponding to a potential of the floating semiconductor region reset by the reset switch; and
wherein the readout circuit includes first and second correlated double sampling circuits for sampling the first and second pixel signals, respectively.

### Claim 2

A solid-state image pickup device comprising: a pixel array including a plurality of pixels arranged in an array:
a control circuit for generating first, second, and third control signals for controlling the a readout circuit for reading the first and second pixel signals from the pixel array in one frame; and
a signal processing unit for processing signals from the readout circuit; wherein each pixel includes: a photoelectric transducer for generating an electric signal from light received thereby;
a floating semiconductor region for accumulating a charge from the photoelectric transducer;
a first charge transfer path extending from the photoelectric transducer to the floating semiconductor region;
a second charge transfer path extending from the photoelectric transducer to the floating semiconductor region; and
an output unit for providing a signal corresponding to a potential in the floating semiconductor region;
wherein one of the first and second charge transfer paths includes a first shutter switch for controlling a transfer of the charge from the photoelectric transducer in response to the first control signal, a first storage diode for accumulating the charge from the photoelectric transducer, and a first transfer switch for controlling a transfer of the charge from the first storage diode to the floating semiconductor region in response to the second control signal;
wherein the other of the first and second charge transfer paths includes a second shutter switch for controlling a transfer of the charge from the photoelectric transducer to the floating semiconductor region through no charge storage unit in response to the third control signal;
wherein the first pixel signal corresponds to a first transfer charge transferred to the floating semiconductor region through the first charge transfer path;
wherein the second pixel signal corresponds to a second transfer charge transferred to the floating semiconductor region through the second charge transfer path;
wherein a first accumulation period for accumulating the charge transferred through the one charge transfer path is longer than a second accumulation period for accumulating the charge transferred through the other charge transfer path;
wherein the signal processing unit includes a signal synthesis unit for synthesizing a synthetic image signal from the first and second pixel signals
wherein the synthetic image signal has a dynamic range wider than that of each of the first and second image signals;
wherein the pixel further comprises a third charge transfer path extending from the photoelectric transducer to the floating semiconductor region;
wherein the third charge transfer path includes a third shutter switch for controlling a transfer of the charge from the photoelectric transducer in response to a fifth control signal, a third storage diode for accumulating the charge from the photoelectric transducer, and a third transfer switch for controlling a transfer of the charge from the third storage diode to the floating semiconductor region in response to a sixth control signal;
wherein the signal processing unit reads a third pixel signal from the pixel array; and
wherein the third pixel signal corresponds to the charge transferred to the floating semiconductor region through the third charge transfer path.
