# US 8,786,742 B2 · Solid-state imager device, drive method of solid-state imager device and camera apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,742 B2 - Document ID: US8786742B2 - Status: Granted - Kind: B2 - Application number: 13/656,011 - Filed: 2012-10-19 - Published: 2013-02-21 - Granted: 2014-07-22 - Earliest claimed: 2005-02-21 - Assignees: Sony Corporation - Applicants: Sony Corporation - Inventors: Keiji Mabuchi; Nobuhiro Karasawa - Web page: https://patentgrep.com/patent/US8786742B2 ## CPC - H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors - H10F 39/026: {Wafer-level processing} - H10F 39/199: {Back-illuminated image sensors} - H10F 39/803: {Pixels having integrated switching, control, storage or amplification elements} - H10F 39/811: {Interconnections} - H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION ## Abstract In a case when a structure of forming a p+ layer on a substrate rear surface side is employed in order to prevent dark current generation from the silicon boundary surface, various problems occur. According to this invention, an insulation film 39 is provided on a rear surface on a silicon substrate 31 and a transparent electrode 40 is further provided thereon, and by applying a negative voltage with respect to the potential of the silicon substrate 31 from a voltage supply source 41 to the insulation film 39 through the transparent electrode 40, positive holes are accumulated on a silicon boundary surface of the substrate rear surface side and a structure equivalent to a state in which a positive hole accumulation layer exists on aforesaid silicon boundary surface is to be created. Thus, various problems in the related art can be avoided. ## Claims ### Claim 1 A solid-state imager device comprising: an insulation film between a wiring layer and a transparent electrode, said transparent electrode touching a voltage supply electrode and said insulation film; a conversion region of a first conductivity type touching said insulation film and said wiring layer, said first conductivity type being opposite to a second conductivity type; a well region of the second conductivity type touching said insulation film and a reference electrode, said conversion region and said wiring layer touching said well region. ### Claim 2 (depends on 1) A solid-state imager device according to claim 1, wherein said reference electrode is configured to receive a reference voltage potential. ### Claim 3 (depends on 2) A solid-state imager device according to claim 2, wherein said reference voltage potential is a ground potential. ### Claim 4 (depends on 1) A solid-state imager device according to claim 1, further comprising: a terminal of a voltage supply configured to supply a voltage potential to said voltage supply electrode. ### Claim 5 (depends on 4) A solid-state imager device according to claim 4, wherein said reference electrode is electrically connected to another terminal of the voltage supply. ### Claim 6 (depends on 4) A solid-state imager device according to claim 4, wherein said voltage potential is a negative voltage when said first conductivity type is N-type, said negative voltage being a voltage not greater than 0 volts. ### Claim 7 (depends on 4) A solid-state imager device according to claim 4, wherein said voltage potential is a positive voltage when said first conductivity type is P-type, said positive voltage being a voltage greater than 0 volts. ### Claim 8 (depends on 1) A solid-state imager device according to claim 1, further comprising: a carrier accumulation region of the second conductivity type between said wiring layer and a charge accumulation region of the first conductivity type, said charge accumulation region and said wiring layer touching said carrier accumulation region. ### Claim 9 (depends on 8) A solid-state imager device according to claim 8, wherein said charge accumulation region is between said carrier accumulation region and said insulation film. ### Claim 10 (depends on 8) A solid-state imager device according to claim 8, wherein said charge accumulation region touches said conversion region. ### Claim 11 (depends on 8) A solid-state imager device according to claim 8, further comprising: a floating diffusion portion of the first conductivity type touching said wiring layer. ### Claim 12 (depends on 11) A solid-state imager device according to claim 11, wherein said floating diffusion portion touches said well region. ### Claim 13 (depends on 11) A solid-state imager device according to claim 11, wherein an impurity concentration of the first conductivity type within said floating diffusion portion is higher than an impurity concentration of the first conductivity type within said conversion region. ### Claim 14 (depends on 13) A solid-state imager device according to claim 13, wherein said impurity concentration of the first conductivity type within said floating diffusion portion is higher than an impurity concentration of the first conductivity type within said charge accumulation region. ### Claim 15 (depends on 14) A solid-state imager device according to claim 14, wherein said impurity concentration of the first conductivity type within said charge accumulation region is higher than an impurity concentration of the first conductivity type within said conversion region. ### Claim 16 (depends on 11) A solid-state imager device according to claim 11, wherein a channel region portion of the conversion region is between said carrier accumulation region and said floating diffusion portion. ### Claim 17 (depends on 16) A solid-state imager device according to claim 16, wherein said channel region portion of the conversion region touches said floating diffusion portion and said carrier accumulation region. ### Claim 18 (depends on 16) A solid-state imager device according to claim 16, further comprising: a gate electrode within said wiring layer, a portion of the wiring layer being between said channel region portion and said gate electrode. ### Claim 19 (depends on 1) A solid-state imager device according to claim 1, wherein said conversion region and said well region are in a semiconductor substrate, said semiconductor substrate being between said insulation film and said wiring layer. ### Claim 20 (depends on 19) A solid-state imager device according to claim 19, wherein said semiconductor substrate is a silicon substrate. ### Claim 21 (depends on 1) A solid-state imager device according to claim 1, wherein said wiring layer is an interlayer insulation film. ### Claim 22 (depends on 1) A solid-state imager device according to claim 1, wherein said insulation film is between said transparent electrode and said conversion region. ### Claim 23 (depends on 1) A solid-state imager device according to claim 1, wherein said insulation film is between said transparent electrode and said well region. ### Claim 24 (depends on 1) A solid-state imager device according to claim 1, wherein said transparent electrode is an indium tin oxide. ### Claim 25 (depends on 1) A solid-state imager device according to claim 1, wherein said insulation film is from the group consisting of a silicon oxide film and a silicon nitride film. ### Claim 26 (depends on 1) A solid-state imager device according to claim 1, wherein positive holes are non-diffusible through said insulation film.