# US 8,786,674 B2 · Method for performing video display control within a video display system, and associated video processing circuit and video display system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,674 B2 - Document ID: US8786674B2 - Status: Granted - Kind: B2 - Application number: 13/130,755 - Filed: 2010-11-26 - Published: 2012-05-31 - Granted: 2014-07-22 - Earliest claimed: 2010-11-26 - Assignees: MediaTek Singapore Pte. Ltd. - Applicants: Guoping Li; Chin-Jung Yang; Geng Li; Te-Chi Hsiao - Inventors: Guoping Li; Chin-Jung Yang; Geng Li; Te-Chi Hsiao - Web page: https://patentgrep.com/patent/US8786674B2 ## CPC - G09G 5/36: characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory - G09G 3/003: {to produce spatial visual effects} - G09G 5/397: Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay (G09G5/02 takes precedence) - G09G 5/399: using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers - H04N 13/161: Encoding, multiplexing or demultiplexing different image signal components (for multi-view video sequence encoding H04N19/597) - H04N 13/189: Recording image signals; Reproducing recorded image signals - H04N 13/398: Synchronisation thereof; Control thereof - H04N 13/00: Stereoscopic video systems; Multi-view video systems; Details thereof - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION ## Abstract A method for performing video display control within a video display system includes: dynamically utilizing two of a plurality of buffers as on-screen buffers for three-dimensional (3D) frames, wherein the plurality of buffers is positioned within the video display system; and during utilizing any of the two of the plurality of buffers as an on-screen buffer, dynamically utilizing at least one other buffer of the plurality of buffers as at least one off-screen buffer for at least one 3D frame. An associated video processing circuit and an associated video display system are also provided. In particular, the video processing circuit is positioned within the video display system, where the video processing circuit operates according to the method. ## Claims ### Claim 1 A method for performing video display control within a video display system, the method comprising: dynamically utilizing two of a plurality of buffers as on-screen buffers for three-dimensional (3D) frames, wherein the plurality of buffers is positioned within the video display system; and during utilizing any of the two of the plurality of buffers as an on-screen buffer, dynamically utilizing at least one other buffer of the plurality of buffers as at least one off-screen buffer for at least one 3D frame; wherein the two of the buffers utilized as two on-screen buffer respectively storing a first left 3D frame to be displayed for a left eye of a user and a first right 3D frame to be displayed for a right eye of the user; and wherein the at least one other buffer utilized as one off-screen buffer alternately stores a second left 3D frame to be displayed for the left eye of the user and a second right 3D frame to be displayed for the right eye of the user. ### Claim 2 (depends on 1) The method of claim 1, wherein the step of dynamically utilizing the two of the plurality of buffers as the on-screen buffers for the 3D frames further comprises: respectively utilizing the two of the plurality of buffers as on-screen buffers in different periods. ### Claim 3 (depends on 2) The method of claim 2, wherein the step of dynamically utilizing the two of the plurality of buffers as the on-screen buffers for the 3D frames further comprises: respectively utilizing the two of the plurality of buffers as on-screen buffers in different periods, with aid of a multiplexer within the video display system, wherein the multiplexer is arranged to multiplex an output of one of the buffers. ### Claim 4 (depends on 2) The method of claim 2, wherein the different periods are different periods of a vertical synchronization signal. ### Claim 5 (depends on 1) The method of claim 1, wherein a number of the plurality of buffers is an odd number. ### Claim 6 (depends on 5) The method of claim 5, wherein the number of the plurality of buffers is equal to three. ### Claim 7 (depends on 5) The method of claim 5, wherein the number of the plurality of buffers is equal to five. ### Claim 8 (depends on 1) The method of claim 1, wherein the step of dynamically utilizing the at least one other buffer of the plurality of buffers as the at least one off-screen buffer for the at least one 3D frame further comprises: utilizing the other(s) of the buffers as off-screen buffer(s). ### Claim 9 (depends on 1) The method of claim 1, further comprising: detecting whether a display device coupled to the video display system is a 3D display device. ### Claim 10 (depends on 1) The method of claim 1, wherein the two of the plurality of buffers and the at least one buffer are alternately utilized as two on-screen buffers and one off-screen buffer. ### Claim 11 (depends on 10) The method of claim 10, further comprises: utilizing the two of the plurality of buffers as an on-screen buffer, and utilizing the at least one other buffer of the plurality of buffers as at least one off-screen buffer during a first period; and during a second period after the first period, utilizing one of the two of the plurality of buffers as the off-screen buffer, utilizing another one of the two of the plurality of buffers as the on-screen buffer, and utilizing the at least one other buffer of the plurality of buffers as one on-screen buffer. ### Claim 12 A video processing circuit, the video processing circuit being positioned within a video display system, the video processing circuit comprising: a controller arranged to control operations of the video processing circuit; a demultiplexer arranged to demultiplex a three-dimensional (3D) video stream into a left video stream and a right video stream; two video decoders arranged to respectively decode the left video stream and the right video stream to generate a plurality of 3D frames; and a buffering module arranged to temporarily store the 3D frames, the buffering module comprising a plurality of buffers, wherein under control of the controller, the buffering module dynamically utilizes two of the plurality of buffers as on-screen buffers for at least a portion of the 3D frames, and under control of the controller, during utilizing any of the two of the plurality of buffers as an on-screen buffer, the buffering module dynamically utilizes at least one other buffer of the plurality of buffers as at least one off-screen buffer for at least one 3D frame; wherein the two of the buffers utilized as two on-screen buffer respectively storing a first left 3D frame to be displayed for a left eye of a user and a first right 3D frame to be displayed for a right eye of the user; and wherein the at least one other buffer utilized as one off-screen buffer alternately stores a second left 3D frame to be displayed for the left eye of the user and a second right 3D frame to be displayed for the right eye of the user. ### Claim 13 (depends on 12) The video processing circuit of claim 12, wherein the buffering module respectively utilizes the two of the plurality of buffers as on-screen buffers in different periods. ### Claim 14 (depends on 13) The video processing circuit of claim 13, further comprising: a multiplexer arranged to multiplex an output of one of the buffers; wherein the buffering module respectively utilizes the two of the plurality of buffers as on-screen buffers in different periods, with aid of the multiplexer. ### Claim 15 (depends on 13) The video processing circuit of claim 13, wherein the different periods are different periods of a vertical synchronization signal. ### Claim 16 (depends on 12) The video processing circuit of claim 12, wherein a number of the plurality of buffers is an odd number. ### Claim 17 (depends on 16) The video processing circuit of claim 16, wherein the number of the plurality of buffers is equal to three. ### Claim 18 (depends on 16) The video processing circuit of claim 16, wherein the number of the plurality of buffers is equal to five. ### Claim 19 (depends on 12) The video processing circuit of claim 12, wherein the buffering module utilizes the other(s) of the buffers as off-screen buffer(s). ### Claim 20 (depends on 12) The video processing circuit of claim 12, further comprising: a display device detector arranged to detect whether a display device coupled to the video display system is a 3D display device. ### Claim 21 (depends on 12) The video processing circuit of claim 12, wherein the two of the plurality of buffers and the at least one buffer are alternately utilized as two on-screen buffers and one off-screen buffer. ### Claim 22 (depends on 21) The video processing circuit of claim 21, wherein under control of the controller, the buffering module further utilizes the two of the plurality of buffers as an on-screen buffer, and utilizing the at least one other buffer of the plurality of buffers as at least one off-screen buffer during a first period; and during a second period after the first period, utilizes one of the two of the plurality of buffers as the off-screen buffer, utilizing another one of the two of the plurality of buffers as the on-screen buffer, and utilizing the at least one other buffer of the plurality of buffers as one on-screen buffer. ### Claim 23 A video display system, comprising: a video processing circuit, comprising: a controller arranged to control operations of the video processing circuit; a demultiplexer arranged to demultiplex a three-dimensional (3D) video stream into a left video stream and a right video stream; two video decoders arranged to respectively decode the left video stream and the right video stream to generate a plurality of 3D frames; and a buffering module arranged to temporarily store the 3D frames, the buffering module comprising a plurality of buffers, wherein under control of the controller, the buffering module dynamically utilizes two of the plurality of buffers as on-screen buffers for at least a portion of the 3D frames, and under control of the controller, during utilizing any of the two of the plurality of buffers as an on-screen buffer, the buffering module dynamically utilizes at least one other buffer of the plurality of buffers as at least one off-screen buffer for at least one 3D frame; wherein the two of the buffers utilized as two on-screen buffer respectively storing a first left 3D frame to be displayed for a left eye of a user and a first right 3D frame to be displayed for a right eye of the user; and wherein the at least one other buffer utilized as one off-screen buffer alternately stores a second left 3D frame to be displayed for the left eye of the user and a second right 3D frame to be displayed for the right eye of the user. ### Claim 24 (depends on 23) The video display system of claim 23, wherein the buffering module respectively utilizes the two of the plurality of buffers as on-screen buffers in different periods. ### Claim 25 (depends on 24) The video display system of claim 24, wherein the video processing circuit further comprises: a multiplexer arranged to multiplex an output of one of the buffers; wherein the buffering module respectively utilizes the two of the plurality of buffers as on-screen buffers in different periods, with aid of the multiplexer. ### Claim 26 (depends on 24) The video display system of claim 24, wherein the different periods are different periods of a vertical synchronization signal. ### Claim 27 (depends on 23) The video display system of claim 23, wherein a number of the plurality of buffers is an odd number. ### Claim 28 (depends on 27) The video display system of claim 27, wherein the number of the plurality of buffers is equal to three. ### Claim 29 (depends on 27) The video display system of claim 27, wherein the number of the plurality of buffers is equal to five. ### Claim 30 (depends on 23) The video display system of claim 23, wherein the buffering module utilizes the other(s) of the buffers as off-screen buffer(s). ### Claim 31 (depends on 23) The video display system of claim 23, wherein the video processing circuit further comprises: a display device detector arranged to detect whether a display device coupled to the video display system is a 3D display device. ### Claim 32 (depends on 23) The video display system of claim 23, wherein the two of the plurality of buffers and the at least one buffer alternately are utilized as two on-screen buffers and one off-screen buffer. ### Claim 33 (depends on 32) The video display system of claim 32, wherein under control of the controller, the buffering module further utilizes the two of the plurality of buffers as an on-screen buffer, and utilizing the at least one other buffer of the plurality of buffers as at least one off-screen buffer during a first period; and during a second period after the first period, utilizes one of the two of the plurality of buffers as the off-screen buffer, utilizing another one of the two of the plurality of buffers as the on-screen buffer, and utilizing the at least one other buffer of the plurality of buffers as one on-screen buffer.