# US 8,786,531 B2 · Pixel circuit and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,531 B2 - Document ID: US8786531B2 - Status: Granted - Kind: B2 - Application number: 13/635,740 - Filed: 2010-11-19 - Published: 2013-01-10 - Granted: 2014-07-22 - Earliest claimed: 2010-03-19 - Assignees: Sharp Kabushiki Kaisha - Applicants: Yoshimitsu Yamauchi - Inventors: Yoshimitsu Yamauchi - Web page: https://patentgrep.com/patent/US8786531B2 ## CPC - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G09G 3/3659: {the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes} - G02F 1/13624: {having more than one switching element per pixel} - G09G 3/3618: {with automatic refresh of the display panel using sense/write circuits} - G09G 3/3655: {Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors} - G09G 2300/0861: with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes - G09G 2300/0876: Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes - G09G 2320/10: Special adaptations of display systems for operation with variable images - G09G 2330/022: in absence of operation, e.g. no data being entered during a predetermined time - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract A display device which realizes constant display having multiple tones with low power consumption is provided. A pixel circuit 2 has an internal node N1 holding a pixel data voltage applied to a display element unit 21, a first switch circuit 22 transferring the pixel data voltage supplied from a data signal line SL to the internal node N1 through a series circuit of first and second transistor elements T1 and T2, a second circuit 23 having a third transistor element T3 which communicates between an intermediate node N2 connected with the first and second transistor elements T1 and T2, and a voltage supply line VSL, and a control circuit 24 formed with a series circuit of a fourth transistor element T4 and a first capacitative element C1, holding the pixel data voltage held in the internal node N1 at one end of the first capacitative element C1 through the fourth transistor element T4, and controlling conduction of the third transistor element T3 by a boost voltage applied to the other end of the first capacitative element C1, and the first and second transistor elements T1 and T2 are controlled individually. ## Claims ### Claim 1 A pixel circuit comprising: a display element unit including a unit liquid crystal display element; an internal node forming part of the display element unit and holding a pixel data voltage applied to the display element unit; a first switch circuit including a series circuit of first and second transistor elements, having one end connected with a data signal line and the other end connected with the internal node, and transferring to the internal node the pixel data voltage supplied from the data signal line through the series circuit; a second switch circuit including a third transistor element, and having one end connected with a predetermined voltage supply line and the other end connected with an intermediate node which is a connection point where the first and second transistor elements in the series circuit are connected in series; and a control circuit formed with a series circuit of a fourth transistor element and a first capacitative element, holding the pixel data voltage held in the internal node, at one end of the first capacitative element through the fourth transistor element, and controlling conduction of the third transistor element by a boost voltage applied to the other end of the first capacitative element, wherein each of the first to fourth transistor elements includes a first terminal, a second terminal and a control terminal that controls conduction between the first and second terminals, the control terminal of the first transistor element is connected with a first scan signal line setting the first transistor element to a conducted state upon an operation of transferring the pixel data voltage to the internal node, the control terminal of the second transistor element is connected with a second scan signal line setting the second transistor element to a conducted state upon an operation of transferring the pixel data voltage to the internal node, the control terminal of the third transistor element, the second terminal of the fourth transistor element, and the one end of the first capacitative element are connected to each other, and form an output node of the control circuit, the first terminal of the fourth transistor element is connected with the internal node, the control terminal of the fourth transistor element is connected with a first control line, the other end of the first capacitative element is connected with a second control line supplying the boost voltage, upon a self-refresh operation of compensating for voltage fluctuation of the pixel data voltage held in the internal node, using a voltage held in the output node, a first control voltage equal to or more than a maximum voltage of the pixel data voltage held in the internal node is applied to the voltage supply line, a voltage setting the first transistor element to a non-conducted state is applied to the first scanning line, and a voltage setting the second transistor element to a conducted state is applied to the second scanning line, and, in a state where the internal node and the output node have the same potential through the fourth transistor element, the fourth transistor element transitions from a conducted state to a non-conducted state, and thereafter the boosting voltage is applied to the other end of the first capacitative element, thereby boosting the voltage of the output node to a second control voltage obtained by adding a threshold voltage of the third transistor element to the pixel data voltage held in the internal node. ### Claim 2 (depends on 1) The pixel circuit according to claim 1, wherein the first switch circuit consists of the series circuit of the first and second transistor elements, and the first terminal of the first transistor element is connected with the data signal line, the second terminal of the first transistor element and the first terminal of the second transistor element are connected with the intermediate node, and the second terminal of the second transistor element is connected with the internal node. ### Claim 3 (depends on 1) The pixel circuit according to claim 1, wherein the second switch circuit consists of the third transistor element, and the first terminal of the third transistor element is connected with the voltage supply line, and the second terminal of the third transistor element is connected with the intermediate node. ### Claim 4 (depends on 1) The pixel circuit according to claim 1, further comprising a second capacitative element having one end connected to the internal node and the other end connected to a third control line or the voltage supply line. ### Claim 5 (depends on 1) A display device in which a plurality of pixel circuits are arranged in a row direction and a column direction to form a pixel circuit array, each of the pixel circuits being the pixel circuit according to claim 1, the data signal line is provided for each of columns, the first scan signal line is provided for each of rows, the one ends of the first switch circuits in the pixel circuits arranged in the same column are connected to the common data signal line, the control terminals of the first transistor elements in the pixel circuits arranged in the same row are connected to the common first scan signal line, the control terminals of the second transistor elements in the pixel circuits arranged in the same row are connected to the common second scan signal line, the one ends of the second switch circuits in the pixel circuits arranged in the same row or the same column are connected to the common voltage supply line, the control terminals of the fourth transistor elements in the pixel circuits arranged in the same row or the same column are connected to the common first control line, the other ends of the first capacitative elements in the pixel circuits arranged in the same row or the same column are connected to the common second control line, the display device comprising: a data signal line drive circuit individually driving the data signal lines; a scan signal line drive circuit individually driving the first scan signal lines and individually or commonly driving the second scan signal lines; a voltage supply line drive circuit individually or commonly driving the voltage supply lines; and a control line drive circuit individually or commonly driving the first control lines and individually or commonly driving the second control lines. ### Claim 6 (depends on 5) The display device according to claim 5, wherein in the pixel circuits arranged in the same row, the one ends of the second switch circuits are connected to the common voltage supply line, in the pixel circuits arranged in the same row, the control terminals of the fourth transistor elements are connected to the common first control line, and in the pixel circuits arranged in the same row, the other ends of the first capacitative elements are connected to the common second control line. ### Claim 7 (depends on 5) The display device according to claim 5, wherein, upon a writing operation of writing pixel data including two tones or more individually in the pixel circuits arranged in one selected row, the scan signal line drive circuit applies a predetermined selected row voltage to the first and second scan signal lines in the selected row to set the first and second transistor elements arranged in the selected row to a conducted state so as to activate the first switch circuits, and applies a predetermined unselected row voltage to the first scan signal line in a row other than the selected row to set the first transistor elements arranged in the row other than the selected row to a non-conducted state so as to deactivate the first switch circuits, and the data signal line drive circuit individually applies a pixel data voltage corresponding to pixel data to be written in the pixel circuit in each column of the selected row, to each of the data signal lines. ### Claim 8 (depends on 7) The display device according to claim 7, wherein, upon the writing operation, the voltage supply line drive circuit applies a first control voltage equal to or more than the maximum voltage of the pixel data voltage held in the internal node, to the voltage supply line connected to the pixel circuits arranged in the selected row, and the control line drive circuit applies a first switch voltage to the first control line connected to the pixel circuits arranged in the selected row, and a first boost voltage to the second control line connected to the pixel circuits arranged in the selected row. ### Claim 9 (depends on 8) The display device according to claim 8, wherein, upon the writing operation, the voltage supply line drive circuit applies the first control voltage to the voltage supply line connected to the pixel circuits arranged in the row other than the selected row, and the control line drive circuit applies the first switch voltage to the first control line connected to the pixel circuits arranged in the row other than the selected row, and the first boost voltage to the second control line connected to the pixel circuits arranged in the row other than the selected row. ### Claim 10 (depends on 8) The display device according to claim 8, wherein the first switch voltage is a sufficient voltage to make the fourth transistor element enter a conducted state, and make the internal node and the output node have the same potential. ### Claim 11 (depends on 5) The display device according to claim 5, wherein, upon the self-refresh operation which is performed, after a writing operation of writing pixel data individually comprising two tones or more in the pixel circuits arranged in one selected row is finished in each row or all rows of the pixel circuit array, with respect to the pixel circuits for which the writing operation is finished, the scan signal line drive circuit applies the unselected row voltage to the first scan signal line in at least one control target row for which the writing operation is finished to set the first transistor elements of the pixel circuits arranged in the control target row to a non-conducted state, and applies the selected row voltage to the second scan signal line in the control target row to set the second transistor elements of the pixel circuits arranged in the control target row to a conducted state, the voltage supply line drive circuit applies a first control voltage equal to or more than the maximum voltage of the pixel data voltage held in the internal node, to the voltage supply line connected to the pixel circuits arranged in the control target row, and, in a state where the control line drive circuit applies a first switch voltage setting the fourth transistor elements to a conducted state, to the first control line connected to the pixel circuits arranged in the control target row so that the internal node and the output node have the same potential, the control line drive circuit applies a second switch voltage setting the fourth transistor elements to a non-conducted state to electrically separate the internal node and the output node, and, subsequently, changes a voltage of the second control line connected to the pixel circuits arranged in the control target row from a first boost voltage to a second boost voltage, and boosts a voltage of the output node to a second control voltage obtained by adding a threshold voltage of the third transistor element to the pixel data voltage held in the internal node by way of capacitive coupling through the first capacitative element. ### Claim 12 (depends on 11) The display device according to claim 11, wherein, upon the self-refresh operation, when a certain period of time passes after the voltage of the second control line connected to the pixel circuits arranged in the control target row is changed from a first boost voltage to a second boost voltage, the control line drive circuit performs a refresh canceling operation of returning the voltage of the second control line connected to the pixel circuits arranged in the control target row from the second boost voltage to the first boost voltage and, subsequently, returning the voltage of the first control line connected to the pixel circuits arranged in the control target row from the second switch voltage to the first switch voltage so as to make the internal node and the output node have the same potential, and when a certain period of time passes after the refresh canceling operation, the control line drive circuit performs at least once or more a repeating operation of changing the voltage of the first control line connected to the pixel circuits arranged in the control target row from the first switch voltage to the second switch voltage, changing the voltage of the second control line connected to the pixel circuits arranged in the control target row from a first boost voltage to a second boost voltage and, subsequently, after a certain period of time passes, executing the refresh canceling operation again. ### Claim 13 (depends on 11) The display device according to claim 11, wherein, upon the self-refresh operation, when a certain period of time passes after the voltage of the second control line connected to the pixel circuits arranged in the control target row is changed from a first boost voltage to a second boost voltage, the control line drive circuit performs a refresh canceling operation of changing the voltage of the second scan signal line connected to the pixel circuits arranged in the control target row from the selected row voltage to the unselected row voltage, and returning the voltage of the second control line connected to the pixel circuits arranged in the control target row from the second boost voltage to the first boost voltage, and when a certain period of time passes after the refresh canceling operation, the control line drive circuit performs at least once or more a repeating operation of changing the voltage of the second scan signal line in the control target row from the unselected row voltage to the selected row voltage, changing the voltage of the second control line connected to the pixel circuits arranged in the control target row from a first boost voltage to a second boost voltage and, subsequently, after a certain period of time passes, executing the refresh canceling operation again. ### Claim 14 (depends on 11) The display device according to claim 11, wherein the control line drive circuit performs a first operation of applying the first switch voltage to the first control line connected to the pixel circuits arranged in the control target row so as to make the internal node and the output node have the same potential upon the writing operation with respect to the pixel circuits arranged in the control target row. ### Claim 15 (depends on 11) The display device according to claim 11, wherein, when the control terminals of the fourth transistor elements of the pixel circuits arranged in the same row are connected to the common first control line and the other ends of the first capacitative elements of the pixel circuits arranged in the same row are connected to the common second control line, every time the writing operation is finished with respect to each row of the pixel circuit array, the self-refresh operation is started for the pixel circuits in the control target row for which the writing operation is finished, without waiting for the writing operation for all rows to be finished. ### Claim 16 (depends on 11) The display device according to claim 11, wherein, when the self-refresh operation is performed after the writing operation is finished for all rows of the pixel circuit array, a first reset voltage equal to or less than a minimum voltage of the pixel data voltage held in the internal node is applied to all of the data signal lines.