# US 8,786,484 B2 · Analogue to digital converter, an integrated circuit and medical device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,484 B2 - Document ID: US8786484B2 - Status: Granted - Kind: B2 - Application number: 13/699,681 - Filed: 2011-05-25 - Published: 2013-06-13 - Granted: 2014-07-22 - Earliest claimed: 2010-05-26 - Assignees: Agency for Science, Technology and Research - Applicants: Jiahao Cheong; Pradeep Basappa Khannur; Kok Lim Chan; Minkyu Je - Inventors: Jiahao Cheong; Pradeep Basappa Khannur; Kok Lim Chan; Minkyu Je - Web page: https://patentgrep.com/patent/US8786484B2 ## CPC - H03M 1/12: Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) - H03M 1/0682: {using a differential network structure, i.e. symmetrical with respect to ground} - H03M 1/466: {using switched capacitors} - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) ## Abstract An analogue to digital converter includes a first input connection to receive a first part of the analogue input signal, a second input connection to receive a second part of the analogue input signal, a first and second plurality of capacitors, each capacitor of the first plurality of capacitors forms a capacitor pair with a corresponding capacitor in the second plurality of capacitors During a sampling period, the first input connection couples the first part of the analogue input signal to a first contact of each capacitor of the first plurality of capacitors and the second input connection couples the second part of the analogue input signal to a first contact of each capacitor of the second plurality of capacitors. Further, a switching array couples a second contact of each capacitor of the first and second plurality of capacitors to a common mode voltage to determine a first bit of a digital output signal. ## Claims ### Claim 1 An analogue-to-digital converter for converting an analogue input signal into a digital output signal, the analogue-to-digital converter comprising: a first input connection configured to receive a first part of the analog input signal; a second input connection configured to receive a second part of the analogue input signal; a first plurality of capacitors and a second plurality of capacitors, each capacitor of the first and second plurality of capacitors having a first contact and a second contact, each capacitor of the first plurality of capacitors having a corresponding capacitor in the second plurality of capacitors to form a plurality of capacitor pairs; a switching array coupled to the second contact of each capacitor in the first and second plurality of capacitors; and, switching logic for controlling the switching array; wherein, during a sampling period of the analogue-to-digital converter, the first input connection is configured to couple the first part of the analogue input signal to the first contact of each capacitor of the first plurality of capacitors, the second input connection is configured to couple the second part of the analogue input signal to the first contact of each capacitor of the second plurality of capacitors, and the switching logic is configured to cause the switching array to couple the second contact of each capacitor of the first and second plurality of capacitors to a common mode voltage to determine a first bit of the digital output signal. ### Claim 2 (depends on 1) The analogue-to-digital converter of claim 1, wherein, during a conversion period of the analogue-to-digital converter, the switching logic is configured to cause the switching array to couple each second contact of at least one capacitor pair to a different one of a first and a second reference voltage, and to couple the other capacitors in capacitor pairs via their second contacts to determine subsequent bits of the digital output signal. ### Claim 3 (depends on 2) The analogue-to-digital converter of claim 2, wherein, during the conversion period of the analogue-to-digital converter, the switching logic is configured to cause the switching array to couple each second contact of a first capacitor pair to a different one of the first and the second reference voltage depending on the determination of the first bit of the digital output signal, and to couple in pairs any succeeding capacitor pairs to determine a second bit of the digital output signal. ### Claim 4 (depends on 3) The analogue-to-digital converter of claim 3, wherein, during the conversion period of the analogue-to-digital converter, the switching logic is configured to cause the switching array to couple each second contact of an ith capacitor pair to a different one of the first and the second reference voltage depending on a determination of an ith bit of the digital output signal, and to couple in pairs any succeeding capacitor pairs to determine an (i+1)th bit of the digital output signal. ### Claim 5 (depends on 2) The analogue-to-digital converter of claim 2, wherein, during the conversion period of the analogue-to-digital converter, the first input connection is configured to decouple the first part of the analogue input signal from the first contact of each capacitor of the first plurality of capacitors, the second input connection is configured to decouple the second part of the analogue input signal from the first contact of each capacitor of the second plurality of capacitors. ### Claim 6 (depends on 1) The analogue-to-digital converter of claim 1, wherein the switching array is configured to selectively couple the second contact of each capacitor in the first plurality of capacitors to one of the first reference voltage, the second reference voltage, the common mode voltage and its corresponding capacitor in the second plurality of capacitors, and to selectively couple the second contact of each capacitor in the second plurality of capacitors to one of the first reference voltage, the second reference voltage, the common mode voltage, and its corresponding capacitor in the first plurality of capacitors. ### Claim 7 (depends on 1) The analogue-to-digital converter of claim 1, further comprising a comparator having a first input terminal coupled to the first contact of each capacitor of the first plurality of capacitors, and a second input terminal coupled to the first contact of each capacitor of the second plurality of capacitors. ### Claim 8 (depends on 7) The analogue-to-digital converter of claim 7, wherein the comparator further comprises an output, wherein the switching logic is configured to control the switching array in dependence on the comparator output. ### Claim 9 (depends on 8) The analogue-to-digital converter of claim 8, wherein the analogue-to-digital converter is configured to determine bits of the digital output signal in dependence on the comparator output. ### Claim 10 (depends on 7) The analogue-to-digital converter of claim 7, wherein the comparator is a time-domain comparator comprising voltage controlled delay circuitry configured to convert a voltage level of the time-domain comparator to a delay of a clock signal, and phase detection circuitry configured to determine which of the signals input on the first input terminal and the second input terminal changes earlier. ### Claim 11 (depends on 1) The analogue-to-digital converter of claim 1, wherein the first plurality of capacitors comprises capacitance values in a non-binary weighted relationship. ### Claim 12 (depends on 1) The analogue-to-digital converter of claim 1, wherein the second plurality of capacitors comprises capacitance values in a non-binary weighted relationship. ### Claim 13 (depends on 1) The analogue-to-digital converter of claim 1, wherein both capacitors of a capacitor pair have the same capacitance. ### Claim 14 (depends on 2) The analogue-to-digital converter of claim 2, wherein the digital output signal comprises N bits and each of the first plurality of capacitors and the second plurality of capacitors comprise more than N+1 capacitors to provide redundancy. ### Claim 15 (depends on 1) The analogue-to-digital converter of claim 1, wherein the second reference voltage is ground. ### Claim 16 (depends on 1) The analogue-to-digital converter of claim 1, further comprising a reset switch, wherein the switching logic is configured to cause the reset switch to regulate the common mode voltage. ### Claim 17 (depends on 1) The analogue-to-digital converter of claim 1, wherein the first bit is a most significant bit of the digital output signal. ### Claim 18 (depends on 1) The analogue-to-digital converter of claim 1, wherein the first part of the analogue input signal and the second part of the analogue input signal comprise the analogue input signal in differential form. ### Claim 19 (depends on 18) The analogue-to-digital converter of claim 18, wherein the first reference voltage is selected to be equal to a common mode voltage of the analogue input signal in differential form, such that capacitors that are coupled in pairs have a value of half of the first reference voltage at their second contact during the conversion period. ### Claim 20 (depends on 1) An integrated circuit comprising the analogue-to-digital converter of claim 1.