# US 8,786,482 B1 · Integrated circuit with pin for setting digital address > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,482 B1 - Document ID: US8786482B1 - Status: Granted - Kind: B1 - Application number: 13/857,919 - Filed: 2013-04-05 - Granted: 2014-07-22 - Earliest claimed: 2012-10-16 - Assignees: Lattice Semiconductor Corporation - Applicants: Lattice Semiconductor Corporation - Inventors: Robert Bartel; Spiro Sassalos - Web page: https://patentgrep.com/patent/US8786482B1 ## CPC - H03K 19/17712: {one of the matrices at least being reprogrammable} - G01R 31/318597: {JTAG or boundary scan test of memory devices (other scan testing of memories G11C29/32)} - G11C 11/413: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction - G11C 16/24: Bit-line control circuits - G11C 17/16: using electrically-fusible links - H03K 19/177: arranged in matrix form - H03K 19/17704: the logic functions being realised by the interconnection of rows and columns - H03K 19/17716: {with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register (H03K19/17712 takes precedence)} - H03M 1/001: {Analogue/digital/analogue conversion} - H03M 1/34: Analogue value compared with reference values (H03M1/48 takes precedence) - H04L 25/0262: {Arrangements for detecting the data rate of an incoming signal} - H04L 41/0806: for initial configuration or provisioning, e.g. plug-and-play - H10W 70/65: Shapes or dispositions of interconnections - H10W 42/60: protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection H10D89/60) - H10W 70/685: comprising multiple insulating layers - H10W 72/00: Interconnections or connectors in packages - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G11C: STATIC STORES (semiconductor memory devices H10B) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract In one embodiment, an integrated circuit includes a pin and a current source for driving current through the pin into an external resistor such as a resistor on a circuit board to generate a pin voltage. The integrated circuit includes an analog-to-digital converter for converting the pin voltage into a digital value, such as an address for the integrated circuit. ## Claims ### Claim 1 An integrated circuit, comprising: a pin; a current source within the integrated circuit configured to drive a current through the pin; and an analog-to-digital converter within the integrated circuit configured to compare a voltage of the pin to a succession of internal voltages to provide a digital value. ### Claim 2 (depends on 1) The integrated circuit of claim 1, wherein the analog-to-digital converter includes a counter for providing a count as the digital value. ### Claim 3 (depends on 2) The integrated circuit of claim 2, wherein the analog-to-digital converter further includes a multiplexer for selecting a tap on a series of resistors responsive to the count. ### Claim 4 (depends on 2) The integrated circuit of claim 2, wherein the analog-to-digital converter further includes a comparator configured to drive an enable signal to the counter responsive to a comparison of the voltage of the pin and the internal voltage. ### Claim 5 (depends on 4) The integrated circuit of claim 4, wherein the analog-to-digital converter further includes a decoder configured to drive a multiplexer responsive to the count. ### Claim 6 (depends on 4) The integrated circuit of claim 4, wherein the counter is configured to increment the count responsive to cycles of a clock. ### Claim 7 (depends on 5) The integrated circuit of claim 5, wherein the analog-to-digital converter further includes a tapped series of resistors, and wherein the multiplexer is configured to select one of the taps responsive to the decoder decoding the count. ### Claim 8 (depends on 7) The integrated circuit of claim 7, wherein integrated circuit is configured to use the count as an address. ### Claim 9 (depends on 8) The integrated circuit of claim 8, wherein the address is an I2C address. ### Claim 10 (depends on 1) The integrated circuit of claim 1, wherein the current source is a fixed current source. ### Claim 11 A method, comprising: driving an internal current generated within an integrated circuit through a pin of the integrated circuit into a resistor external to the integrated circuit to generate a pin voltage on the pin; and in the integrated circuit, converting the pin voltage into a digital value, wherein converting the pin voltage into a digital value comprises comparing the pin voltage to a succession of different voltages within the integrated circuit. ### Claim 12 (depends on 11) The method of claim 11, wherein comparing the pin voltage to a succession of different voltages continues until one of the different voltages is greater than the pin voltage. ### Claim 13 (depends on 11) The method of claim 11, further comprising successively selecting taps on a series of resistors to provide the succession of different voltages. ### Claim 14 (depends on 11) The method of claim 11, wherein converting the pin voltage into a digital value comprises counting a clock cycle for each successive different voltage. ### Claim 15 (depends on 13) The method of claim 13, wherein successively selecting taps on a series of resistors comprises commanding a multiplexer to successively select the taps. ### Claim 16 An integrated circuit, comprising: a pin; a current source within the integrated circuit configured to drive a current through the pin; and an analog-to-digital converter within the integrated circuit, the analog-to-digital converter including: a comparator configured to compare a voltage on the pin to an internal voltage; a counter responsive to the comparator to provide a digital value; and a multiplexer responsive to the counter and configured to select the internal voltage for comparison to the voltage on the pin. ### Claim 17 (depends on 16) The integrated circuit of claim 16 including a decoder coupled between the counter and the multiplexer and configured to decode the digital value of the counter to control the selection of the internal voltage by the multiplexer. ### Claim 18 (depends on 16) The integrated circuit of claim 16, wherein the analog-to-digital converter further includes a tapped series of resistors, and wherein the multiplexer is configured to select one of the taps in selecting the internal voltage. ### Claim 19 (depends on 16) The integrated circuit of claim 16, wherein the counter is configured to provide a count signal in response to the comparator and cycles of a clock. ### Claim 20 (depends on 16) The integrated circuit of claim 16, wherein the multiplexer is configured to select a succession of different internal voltages in response to changes in a count signal of the counter.