# US 8,786,475 B2 · Input configuration for analog to digital converter > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,475 B2 - Document ID: US8786475B2 - Status: Granted - Kind: B2 - Application number: 13/498,513 - Filed: 2010-08-28 - Published: 2012-12-13 - Granted: 2014-07-22 - Earliest claimed: 2009-09-28 - Assignees: Hittite Microwave Corporation - Applicants: Bjornar Hernes - Inventors: Bjornar Hernes - Web page: https://patentgrep.com/patent/US8786475B2 ## CPC - H03M 1/1245: {Details of sampling arrangements or methods} - G11C 27/024: {using a capacitive memory element (G11C27/04 takes precedence)} - H03M 1/1215: {using time-division multiplexing} - H03M 1/164: {the steps being performed sequentially in series-connected stages (H03M1/161 takes precedence)} - H03M 1/44: Sequential comparisons in series-connected stages with change in value of analogue signal - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A circuit includes an input, two or more sampling capacitors each in a different channel, means for connecting each sampling capacitor to the input, means for discharging the sampling capacitors to a given voltage in a reset phase, and means to use the voltage across the sampling capacitor for further processing in a hold phase. The two sampling capacitors operate in anti-phase such that the reset phase and sampling phase of one channel are performed in the time period the other channel is in the hold phase. ## Claims ### Claim 1 A circuit comprising: an input; at least two sampling capacitors arranged in at least two different channels, each sampling capacitor being coupled to the input when in a sampling phase for storing a value of an input signal, the sampling capacitors each having a reset phase to provide a given voltage to the sampling capacitor prior to the sampling phase, and each sampling capacitor having a hold phase following the sampling phase for further processing of the stored value of the input signal, and wherein the sampling capacitors operate in anti-phase to each other such that the reset phase and sampling phase of one channel are performed when the other channel is in a hold phase or idle. ### Claim 2 (depends on 1) The circuit according to claim 1 wherein the circuit comprises a first stage of a pipelined ADC. ### Claim 3 (depends on 1) The circuit according to claim 1 wherein the circuit comprises part of a sample-and-hold amplifier. ### Claim 4 (depends on 1) The circuit according to claim 1 wherein the circuit comprises part of a track-and-hold amplifier. ### Claim 5 (depends on 1) The circuit according to claim 1 wherein the circuit comprises part of an input stage of an ADC. ### Claim 6 (depends on 1) The circuit according to claim 1 further comprising a differential configuration. ### Claim 7 A circuit comprising: an input; at least two sampling capacitors arranged in two different channels, the sampling capacitors coupled to the input in a sampling phase for storing a value of an input signal; the sampling capacitors also having a reset phase to provide a given voltage to the sampling capacitor prior to the sampling phase, and the sampling capacitors having a hold phase following the sampling phase for further processing of the stored value of the input signal; and an amplifier comprising one input stage per sampling capacitor and a common output stage, wherein the sampling capacitors anti-phase with respect to each other such that the reset phase and sampling phase of one channel are performed when the other channel is in a hold phase or idle. ### Claim 8 (depends on 7) The circuit according to claim 7 wherein the circuit comprises a first stage of a pipelined ADC. ### Claim 9 (depends on 7) The circuit according to claim 7 where the circuit comprises part of a sample-and-hold amplifier. ### Claim 10 (depends on 7) The circuit according to claim 7 where the circuit comprises part of a track-and-hold amplifier. ### Claim 11 (depends on 7) The circuit according to claim 7 wherein the circuit comprises part of an input stage of an ADC. ### Claim 12 (depends on 7) The circuit according to claim 7 further comprising a differential configuration. ### Claim 13 A method of processing an input signal in a circuit comprising an input and two sampling capacitors, each arranged in a separate channel, the method comprising: (a) discharging each sampling capacitor to a given voltage in a reset phase; (b) connecting each sampling capacitor to the input and storing a value of the input signal at the sampling capacitor in a sampling phase following the reset phase; (c) processing the stored value of the input signal in a hold phase after the sampling phase; and (d) repeating steps (a) through (c) a plurality of times; wherein the sampling capacitors anti-phase with respect to each other such that the reset phase and sampling phase of one channel occur when the other channel is in a hold phase or idle.