# US 8,786,374 B2 · Error detection at an oscillator

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- Number: US 8,786,374 B2
- Document ID: US8786374B2
- Status: Granted
- Kind: B2
- Application number: 13/550,676
- Filed: 2012-07-17
- Published: 2014-01-23
- Granted: 2014-07-22
- Earliest claimed: 2012-07-17
- Assignees: Freescale Semiconductor, Inc.
- Applicants: Jon S. Choy
- Inventors: Jon S. Choy
- Web page: https://patentgrep.com/patent/US8786374B2

## CPC

- H03K 3/0315: {Ring oscillators}
- G01R 31/2824: {testing of oscillators or resonators}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

An error detection system employs a chain of delay elements connected in an open loop configuration. To determine whether the oscillator is operating within a specified set of parameters, the error detection system applies a start pulse to an input of the open-loop chain of delay elements. The error detection system compares the resulting output signal with the output of the oscillator. If the oscillator has locked onto a harmonic of the intended output frequency, the comparison of the output signals will indicate an error.

## Claims

### Claim 1

A method, comprising:
generating an output signal at an open-loop chain of delay elements;
determining an oscillator is locked to a harmonic of a desired frequency based on the output signal; and
resetting the oscillator in response to determining the oscillator is locked to the harmonic.

### Claim 2 (depends on 1)

The method of claim 1, further comprising determining the oscillator is locked to the harmonic based on a comparison between the output signal of the open-loop chain of delay elements and an output signal of the oscillator.

### Claim 3 (depends on 1)

The method of claim 1, wherein determining the oscillator is locked to the harmonic comprises:
enabling a counter based on the output signal of the open-loop chain of delay elements;
asserting a signal to change a value stored at the counter based on an output signal of the oscillator; and
determining the oscillator is locked to the harmonic based on the value stored at the counter.

### Claim 4 (depends on 3)

The method of claim 3, wherein enabling the counter comprises enabling the counter based on a logical AND function of the output signal of the open-loop chain of delay elements and a start pulse.

### Claim 5 (depends on 4)

The method of claim 4, wherein generating the output signal of the open-loop chain of delay elements comprises applying the start pulse to an input of the open-loop chain of delay elements to generate the output signal.

### Claim 6 (depends on 4)

The method of claim 4, further comprising generating the start pulse at a control module synchronized with the output signal of the oscillator.

### Claim 7 (depends on 1)

The method of claim 1, further comprising setting an indicator at a processor in response to determining the oscillator is locked to the harmonic.

### Claim 8 (depends on 1)

The method of claim 1, wherein the oscillator comprises a plurality of delay elements, the delay elements of the oscillator having a same circuit configuration as the delay elements of the open loop chain of delay elements.

### Claim 9

A method, comprising:
enabling a counter based on an output signal of an open-loop chain of delay elements;
adjusting the counter based on an output of an oscillator;
detecting the oscillator is locked to a harmonic of a desired frequency based on a value of the counter; and
resetting the oscillator in response to determining the oscillator is locked to the harmonic.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
enabling the counter based on a logical AND function of the output signal and a start pulse generated at a control module.

### Claim 11 (depends on 10)

The method of claim 10, wherein synchronizing the control module comprises generating a signal based on the output of the oscillator, the signal having a lower frequency than the output of the oscillator, and synchronizing the control module using the first signal.

### Claim 12 (depends on 11)

The method of claim 11, wherein synchronizing the control module using the signal comprises synchronizing the control module using the first signal in response to determining an error in operation of the control module.

### Claim 13

A device, comprising:
an oscillator;
an open-loop chain of delay elements; and
an error detection module to:
determine the oscillator is locked to a harmonic of a desired frequency based on the output signal of the oscillator and an output signal of the open-loop chain of delay elements; and
reset the oscillator in response to determining the oscillator is locked to the harmonic.

### Claim 14 (depends on 13)

The device of claim 13, wherein the error detection module determines the oscillator is locked to the harmonic based on a comparison between the output signal of the open-loop chain of delay elements and an output signal of the oscillator.

### Claim 15 (depends on 13)

The device of claim 13, wherein the error detection module comprises a counter, the counter comprising:
an enable input coupled to an output of the open-loop chain of delay elements;
an adjustment input coupled to an output of the oscillator, the counter to adjust a stored value in response to assertion of a signal at the adjustment input when a signal at the enable input is asserted; and
wherein the error detection module is to determine the oscillator is locked to the harmonic based on the stored value.

### Claim 16 (depends on 13)

The device of claim 13, wherein the error detection module further comprises a counter and a logic circuit, the logic circuit to perform an AND function comprising an input to receive a start pulse, an input coupled to the output of the open-loop delay chain, and an output coupled to the enable input of the counter.

### Claim 17 (depends on 16)

The device of claim 16, wherein the open-loop chain of delay elements comprises an input to receive the start pulse.

### Claim 18 (depends on 16)

The device of claim 16, wherein the error detection module comprises a control module to generate the start pulse, the control module synchronized based on the output signal of the oscillator.

### Claim 19 (depends on 13)

The device of claim 13, wherein the oscillator comprises a plurality of delay elements, the delay elements of the oscillator having a same circuit configuration as the delay elements of the open loop chain of delay elements.