# US 8,786,371 B2 · Apparatus and methods for voltage converters > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,371 B2 - Document ID: US8786371B2 - Status: Granted - Kind: B2 - Application number: 13/671,022 - Filed: 2012-11-07 - Published: 2013-05-23 - Granted: 2014-07-22 - Earliest claimed: 2011-11-18 - Assignees: Skyworks Solutions, Inc.; Nujira Limited - Applicants: Skyworks Solutions, Inc.; Nujira Ltd - Inventors: Peter Harris Robert Popplewell; Jakub F Pingot; Florinel G Balteanu; Martin Wilson; Mark Tuckwell - Web page: https://patentgrep.com/patent/US8786371B2 ## CPC - H03F 1/0227: {using supply converters} - H02M 3/156: with automatic control of output voltage or current, e.g. switching regulators - H02M 3/158: including plural semiconductor devices as final control devices for a single load - H03F 1/0211: {with control of the supply voltage or current} - H03F 1/025: {by using a signal derived from the input signal} - H03F 3/19: with semiconductor devices only - H03F 3/193: with field-effect devices (H03F3/195 takes precedence) - H03F 3/195: in integrated circuits - H03F 3/21: with semiconductor devices only {(H03F3/245 takes precedence)} - H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)} - H03F 2200/102: A non-specified detector of a signal envelope being used in an amplifying circuit - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F 2203/21106: An input signal being distributed in parallel over the inputs of a plurality of power amplifiers - H03F: AMPLIFIERS - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract Apparatus and methods for voltage converters are provided. In one embodiment, a voltage conversion system includes a bypass circuit and a voltage converter including an inductor and a plurality of switches configured to control a current through the inductor. The bypass circuit includes a first p-type field effect transistor (PFET), a second PFET, a first n-type field effect transistor (NFET), and a second NFET. The first and second NFET transistors and the first and second PFET transistors are electrically connected between a first end and a second end of the inductor such that a source of the first PFET transistor and a drain of the first NFET transistor are electrically connected to the first end of the inductor and such that a drain of the second PFET transistor and a source of the second NFET transistor are electrically connected to the second end of the inductor. ## Claims ### Claim 1 A voltage conversion system comprising: a voltage converter including an inductor and a plurality of switches configured to control a current through the inductor; and a bypass circuit including a first p-type field effect transistor (PFET), a second PFET, a first n-type field effect transistor (NFET), and a second NFET, the first and second NFET transistors and the first and second PFET transistors electrically connected between a first end and a second end of the inductor such that a source of the first PFET transistor and a drain of the first NFET transistor are electrically connected to the first end of the inductor and such that a drain of the second PFET transistor and a source of the second NFET transistor are electrically connected to the second end of the inductor. ### Claim 2 (depends on 1) The voltage conversion system of claim 1 wherein a drain of the first PFET transistor is electrically connected to a source of the second PFET transistor, to a source of the first NFET transistor, and to a drain of the second NFET transistor. ### Claim 3 (depends on 1) The voltage conversion system of claim 1 wherein a body of the first PFET transistor is electrically connected to a battery voltage and a body of the first NFET transistor is electrically connected to a ground voltage. ### Claim 4 (depends on 3) The voltage conversion system of claim 3 wherein a body of the second PFET transistor is electrically connected to a boost voltage, the boost voltage having a magnitude greater than the battery voltage. ### Claim 5 (depends on 4) The voltage conversion system of claim 4 wherein a body of the second NFET transistor is electrically connected to a switchable voltage, the switchable voltage configured to be switched between a voltage equal to about the ground voltage and a voltage greater than the ground voltage based on a magnitude of an output voltage generated by the voltage converter. ### Claim 6 (depends on 5) The voltage conversion system of claim 5 further comprising a first level shifter and a second level shifter, the first level shifter configured to generate gate control signals for a gate of the first PFET transistor and for a gate of the first NFET transistor, and the second level shifter configured to generate gate control signals for a gate of the second PFET transistor and for a gate of the second NFET transistor. ### Claim 7 (depends on 6) The voltage conversion system of claim 6 wherein the first level shifter is electrically powered using the battery voltage and the ground voltage and the second level shifter is electrically powered using the boost voltage and the switchable voltage so as to prevent the second PFET transistor from breakdown between the gate and the drain. ### Claim 8 (depends on 5) The voltage conversion system of claim 5 further comprising an inverter and a low drop-out regulator configured to generate a regulated voltage, the inverter electrically powered using the regulated voltage and the ground voltage, the output of the inverter configured to generate the switchable voltage based on an input protection control signal. ### Claim 9 (depends on 3) The voltage conversion system of claim 3 further comprising a diode having an anode electrically connected to the ground supply and a cathode electrically connected to the drain of the first NFET transistor, the diode configured to protect the first NFET transistor from damage when the first end of the inductor has a voltage less than the ground voltage. ### Claim 10 (depends on 1) The voltage conversion system of claim 1 wherein the plurality of switches of the voltage converter includes a switch having a first end electrically connected to the first end of the inductor and a second end electrically connected to a ground supply. ### Claim 11 (depends on 10) The voltage conversion system of claim 10 further comprising an electrical component disposed in an electrical path between the second end of the switch and the ground supply, the electrical component having a resistance. ### Claim 12 (depends on 10) The voltage conversion system of claim 10 wherein a body of the first NFET transistor is electrically connected to the second end of the switch. ### Claim 13 (depends on 1) The voltage conversion system of claim 1 wherein the voltage converter includes a switch control block configured to control the plurality of switches to generate a plurality of output voltages. ### Claim 14 A bypass circuit for a voltage converter including an inductor and a plurality of switches configured to control a current through the inductor, the bypass circuit comprising: a first p-type field effect transistor (PFET) transistor; a first n-type field effect transistor (NFET) transistor having a drain electrically connected to a source of the first PFET transistor and to a first end of the inductor; a second PFET transistor having a source electrically connected to a drain of the first PFET transistor; and a second NFET transistor having a drain electrically connected to a source of the first NFET transistor and a source electrically connected to a drain of the second PFET transistor and to a second end of the inductor. ### Claim 15 (depends on 14) The bypass circuit of claim 14 wherein the drain of the first PFET transistor is electrically connected to the source of the first NFET transistor and to the drain of the second NFET transistor. ### Claim 16 (depends on 14) The bypass circuit of claim 14 wherein the first and second PFETs are each p-type metal oxide semiconductor (PMOS) transistors and the first and second NFETs are each n-type metal oxide semiconductor (NMOS) transistors. ### Claim 17 (depends on 14) The bypass circuit of claim 14 wherein a body of the first PFET transistor is electrically connected to a battery voltage and a body of the first NFET transistor is electrically connected to a ground voltage. ### Claim 18 (depends on 17) The bypass circuit of claim 17 wherein a body of the second PFET transistor is electrically connected to a boost voltage, the boost voltage having a magnitude greater than the battery voltage. ### Claim 19 (depends on 18) The bypass circuit of claim 18 wherein a body of the second NFET transistor is electrically connected to a switchable voltage, the switchable voltage configured to be switchable between a voltage equal to about the ground voltage and a voltage greater than the ground voltage. ### Claim 20 (depends on 19) The bypass circuit of claim 19 further comprising a first level shifter and a second level shifter, the first level shifter configured to generate gate control signals for a gate of the first PFET transistor and for a gate of the first NFET transistor, and the second level shifter configured to generate gate control signals for a gate of the second PFET transistor and for a gate of the second NFET transistor. ### Claim 21 (depends on 20) The bypass circuit of claim 20 wherein the first level shifter is electrically powered using the battery voltage and the ground voltage and the second level shifter is electrically powered using the boost voltage and the switchable voltage so as to prevent the second PFET transistor from breakdown between the gate and the drain. ### Claim 22 (depends on 17) The bypass circuit of claim 17 further comprising a diode having an anode electrically connected to the ground supply and a cathode electrically connected to the drain of the first NFET transistor, the diode configured to protect the first NFET transistor from breakdown between the body and the drain when the first end of the inductor has a voltage less than the ground voltage. ### Claim 23 A method of reducing ringing in a voltage converter, the method comprising: generating a plurality of output voltages using the voltage converter, the voltage converter including an inductor and a plurality of switches for controlling a current through the inductor; and bypassing the inductor using a bypass circuit, the bypass circuit including a first p-type field effect transistor (PFET), a second PFET, a first n-type field effect transistor (NFET), and a second NFET, the first and second NFET transistors and the first and second PFET transistors electrically connected between a first end and a second end of the inductor such that a source of the first PFET transistor and a drain of the first NFET transistor are electrically connected to the first end of the inductor and such that a drain of the second PFET transistor and a source of the second NFET transistor are electrically connected to the second end of the inductor. ### Claim 24 (depends on 23) The method of claim 23 further comprising biasing a body of the second PFET transistor at a voltage that is greater than a voltage of a body of the first PFET transistor. ### Claim 25 (depends on 24) The method of claim 24 further comprising biasing a body of the first NFET transistor to a ground voltage and biasing a body of the second NFET transistor to a switchable voltage. ### Claim 26 (depends on 24) The method of claim 24 further comprising increasing the voltage of the switchable voltage above that of the ground voltage when generating at least one of the plurality of output voltages. ### Claim 27 A wireless device comprising: a battery having a battery voltage; a voltage converter including an inductor and a plurality of switches configured to control a current through the inductor, the voltage converter configured to generate a plurality of output voltages from the battery voltage; and a bypass circuit including a first p-type field effect transistor (PFET), a second PFET, a first n-type field effect transistor (NFET), and a second NFET, the first and second NFET transistors and the first and second PFET transistors electrically connected between a first end and a second end of the inductor such that a source of the first PFET transistor and a drain of the first NFET transistor are electrically connected to the first end of the inductor and such that a drain of the second PFET transistor and a source of the second NFET transistor are electrically connected to the second end of the inductor. ### Claim 28 (depends on 27) The wireless device of claim 27 wherein a drain of the first PFET transistor is electrically connected to a source of the second PFET transistor, to a source of the first NFET transistor, and to a drain of the second NFET transistor. ### Claim 29 (depends on 28) The wireless device of claim 28 wherein a body of the first PFET transistor is electrically connected to the battery voltage and a body of the first NFET transistor is electrically connected to a ground voltage. ### Claim 30 (depends on 29) The wireless device of claim 29 wherein a body of the second PFET transistor is electrically connected to a boost voltage, the boost voltage having a magnitude greater than the battery voltage. ### Claim 31 (depends on 30) The wireless device of claim 30 wherein a body of the second NFET transistor is electrically connected to a switchable voltage, the switchable voltage configured to be switched between a voltage equal to about the ground voltage and a voltage greater than the ground voltage based on a magnitude of one of the plurality of output voltages generated by the voltage converter. ### Claim 32 (depends on 31) The wireless device of claim 31 further comprising a first level shifter and a second level shifter, the first level shifter configured to generate gate control signals for a gate of the first PFET transistor and for a gate of the first NFET transistor, and the second level shifter configured to generate gate control signals for a gate of the second PFET transistor and for a gate of the second NFET transistor. ### Claim 33 (depends on 32) The wireless device of claim 32 wherein the first level shifter is electrically powered using the battery voltage and the ground voltage and the second level shifter is electrically powered using the boost voltage and the switchable voltage so as to prevent the second PFET transistor from breakdown between the gate and the drain. ### Claim 34 (depends on 27) The wireless device of claim 27 further comprising a plurality of output switches and a voltage adjustment module, the plurality of output switches configured to select amongst the plurality of output voltages, and the voltage adjustment module configured to generate a power amplifier supply voltage by adjusting a voltage magnitude of the selected output voltage. ### Claim 35 (depends on 34) The wireless device of claim 34 further comprising a power amplifier configured to receive the power amplifier supply voltage. ### Claim 36 (depends on 34) The wireless device of claim 34 wherein the plurality of output voltages includes at least one output voltage having a magnitude greater than a magnitude of the battery voltage. ### Claim 37 (depends on 34) The wireless device of claim 34 wherein the plurality of output voltages includes at least one output voltage having a magnitude less than a magnitude of the battery voltage.