# US 8,786,358 B2 · Reference voltage circuit and semiconductor integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,358 B2 - Document ID: US8786358B2 - Status: Granted - Kind: B2 - Application number: 13/036,956 - Filed: 2011-02-28 - Published: 2011-09-22 - Granted: 2014-07-22 - Earliest claimed: 2010-03-19 - Assignees: Spansion LLC - Applicants: Yoshiyuki Endo; Kenta Aruga; Suguru Tachibana; Koji Okada - Inventors: Yoshiyuki Endo; Kenta Aruga; Suguru Tachibana; Koji Okada - Web page: https://patentgrep.com/patent/US8786358B2 ## CPC - G05F 3/245: {producing a voltage or current as a predetermined function of the temperature} - G05F 3/30: Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities (G05F3/26 takes precedence) - G05F: SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES ## Abstract A reference voltage circuit includes a first amplifier configured to output a reference voltage, a second amplifier coupled to the first amplifier, an offset adjustment voltage generation circuit, a first load device and a first pn junction device, and second and third load devices and a second pn junction device. The offset adjustment voltage generation circuit is configured to generate a voltage which is input to the third and fourth input terminals of the second amplifier, and reduce an offset voltage between the first and second input terminals of the first amplifier through the second amplifier. The first input terminal is coupled to a coupling node of the first load device and the first pn junction device, and the second input terminal is coupled to a coupling node of the second load device and the third load device. ## Claims ### Claim 1 A reference voltage circuit, comprising: a first amplifier, including first and second input terminals and provided between a first power source line and a second power source line, configured to output a reference voltage; a second amplifier coupled to the first amplifier, including third and fourth input terminals and provided between the first power source line and the second power source line; an offset adjustment voltage generation circuit configured to generate first and second voltages which are input to the third and fourth input terminals of the second amplifier, and reduce an offset voltage between the first and second input terminals of the first amplifier through the second amplifier; a first load device and a first pn junction device, coupled in series between a reference voltage line to which the reference voltage is applied and the second power source line; and second and third load devices and a second pn junction device, coupled in series between the reference voltage line and the second power source line, wherein the first input terminal is coupled to a coupling node of the first load device and the first pn junction device, and the second input terminal is coupled to a coupling node of the second load device and the third load device, and the offset adjustment voltage generation circuit comprises: a resistor group including a plurality of resistors which are coupled in series between the reference voltage line and the second power source line; and a switch group including a plurality of switches which are coupled to nodes between resistors of the resistor group, wherein the first voltage which is input to the third input terminal is taken out from a fixed node in the nodes between the resistors, and the second voltage which is input to the fourth input terminal is taken out from any node in the nodes between the resistors which is selected by the switch group. ### Claim 2 (depends on 1) The reference voltage circuit as claimed in claim 1, wherein the first amplifier includes a two-stage configuration of a first amplification circuit and a second amplification circuit, the first amplification circuit includes an input differential circuit and a fourth load device configured to convert two current outputs of the input differential circuit to voltage, the second amplifier includes a one-stage configuration of a third amplification circuit, and the current output of the third amplification circuit is added to the two current outputs of the input differential circuit of the first amplification circuit. ### Claim 3 (depends on 2) The reference voltage circuit as claimed in claim 2, wherein the first pn junction device is a first PNP transistor, the second pn junction device is a second PNP transistor, the first load device is a first resistor, the second load device is a second resistor, the third load device is a third resistor, and the fourth load device is a load transistor, the first PNP transistor and the second PNP transistor are biased to different current densities, and the offset adjustment voltage generation circuit generates a voltage which is input to the third and fourth input terminals so that an offset voltage between the first and second input terminals is cancelled out. ### Claim 4 (depends on 3) The reference voltage circuit as claimed in claim 3, wherein the offset adjustment voltage generation circuit comprises: a second switch group which includes a plurality of switches which are coupled to the nodes between resistors of the resistor group, wherein the first voltage which is input to the third input terminal is taken out from any first node in the nodes between the resistors selected by the switch group, and the second voltage which is input to the fourth input terminal is taken out from any second node in the nodes between the resistors which is selected by the second switch group. ### Claim 5 (depends on 3) The reference voltage circuit as claimed in claim 3, wherein the offset adjustment voltage generation circuit comprises: a second resistor group including a plurality of resistors which are coupled in series between the reference voltage line and the second power source line; and a second switch group including a plurality of switches which are coupled to the nodes between resistors of the second resistor group, wherein the first voltage which is input to the third input terminal is taken out from any first node in the nodes between the resistors selected by the switch group, and the second voltage which is input to the fourth input terminal is taken out from any second node in the nodes between the resistors which is selected by the second switch group. ### Claim 6 (depends on 1) The reference voltage circuit as claimed in claim 1, wherein the offset adjustment voltage generation circuit makes a potential difference of input voltages to the third and fourth input terminals of the second amplifier zero or a given fixed value when turning on a power, and when an access of a nonvolatile memory, which stores data for controlling the switches to adjust the first and second voltages of the third and fourth input terminals, is enabled, the offset voltage between the first and second input terminals of the first amplifier is controlled to zero. ### Claim 7 (depends on 6) The reference voltage circuit as claimed in claim 6, wherein, when turning on a power, the potential difference of the first and second voltages to the third and fourth input terminals of the second amplifier is controlled to zero or a given fixed value by using an output of a power on reset circuit. ### Claim 8 A semiconductor integrated circuit comprising: a reference voltage circuit including a first amplifier, including first and second input terminals and provided between a first power source line and a second power source line, configured to output a reference voltage; a low voltage detection circuit configured to monitor a first power source voltage of the first power source line; a power on reset circuit configured to generate a given signal when turning on a power; an internal circuit; and a regulator circuit configured to generate an internal voltage which makes the internal circuit operate from the first power source voltage of the first power source line which is supplied from an outside, wherein the reference voltage circuit further comprises: a second amplifier coupled to the first amplifier, including third and fourth input terminals and provided between the first power source line and the second power source line; an offset adjustment voltage generation circuit configured to generate avoltage first and second voltages which are input to the third and fourth input terminals of the second amplifier, and reduce the offset voltage between the first and second input terminals of the first amplifier through the second amplifier; a first load device and a first pn junction device, coupled in series between a reference voltage line to which the reference voltage is applied and the second power source line; second and third load devices and a second pn junction device, coupled inseries between the reference voltage line and the second power source line; and a nonvolatile memory configured to store data which controls the switches in the offset adjustment voltage generation circuit, adjust the first and second voltages which are input to the third and fourth input terminals, and make the offset voltage between the first and second input terminals of the first amplifier zero, wherein the first input terminal is coupled to a coupling node of the first load device and the first pn junction device, and the second input terminal is coupled to a coupling node of the second load device and the third load device. ### Claim 9 (depends on 8) The semiconductor integrated circuit as claimed in claim 8, wherein the nonvolatile memory is a flash memory, the flash memory is supplied with the internal voltage generated at the regulator circuit, and a reference voltage of the regulator circuit is an output voltage of the reference voltage circuit. ### Claim 10 (depends on 9) The semiconductor integrated circuit as claimed in claim 9, the semiconductor integrated circuit further comprising: a power on reset circuit configured to make a potential difference of the first and second voltages to the third and fourth input terminals of the second amplifier in the reference voltage circuit zero or a given fixed value when turning on a power. ### Claim 11 (depends on 10) The semiconductor integrated circuit as claimed in claim 10, wherein the power on reset circuit uses a signal of a startup circuit which performs control so that an emitter potential of the first PNP transistor in the reference voltage circuit does not stop at OV when turning on a power. ### Claim 12 (depends on 11) The semiconductor integrated circuit as claimed in claim 11, wherein the power on reset circuit uses the internal voltage generated by the regulator circuit based on an output voltage of the reference voltage circuit. ### Claim 13 (depends on 8) The semiconductor integrated circuit as claimed in claim 8, wherein the regulator circuit uses voltage from the offset adjustment voltage generation circuit at the reference voltage circuit. ### Claim 14 A reference voltage circuit comprising: a first amplifier, including first and second input terminals and configured to output a reference voltage; a second amplifier coupled to the first amplifier, such that the second amplifier and the first amplifier share a same node, the second amplifier including third and fourth input terminals; a feedback circuit configured to receive the reference voltage and provide a first and second voltage to the first and second input terminals respectively; and a voltage generation circuit comprising a plurality of resistors and a plurality of switches, wherein the voltage generation circuit is configured to provide a third and fourth voltage to the third and fourth input terminals, respectively, based at least on the reference voltage and on one or more switching states of the plurality of switches. ### Claim 15 (depends on 14) The reference voltage circuit of claim 14, wherein the feedback circuit comprises: a first load device and a first pn junction device, coupled to a reference voltage line to which the reference voltage is applied; and second and third load devices and a second pn junction device, coupled to the reference voltage line. ### Claim 16 (depends on 15) The reference voltage circuit of claim 15, wherein the first input terminal is coupled to a node between the first load device and the first pn junction device, and the second input terminal is coupled to a node between the second load device and the third load device. ### Claim 17 (depends on 14) The reference voltage circuit of claim 14, wherein the plurality of resistors are coupled in series and further coupled to a reference voltage line to which the reference voltage is applied. ### Claim 18 (depends on 15) The reference voltage circuit of claim 15, wherein each of the plurality of switches is coupled to a node between two resistors of the plurality of resistors. ### Claim 19 (depends on 14) The reference voltage circuit of claim 14, wherein the one or more switching states are determined based on control signals associated with a memory. ### Claim 20 (depends on 14) The reference voltage circuit of claim 14, wherein the voltage generation circuit is further configured to reduce an offset between the first voltage and the second voltage via the second amplifier.