# US 8,786,345 B2 · Single-trigger low-energy flip-flop circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,345 B2 - Document ID: US8786345B2 - Status: Granted - Kind: B2 - Application number: 13/852,987 - Filed: 2013-03-28 - Published: 2013-08-22 - Granted: 2014-07-22 - Earliest claimed: 2011-04-27 - Assignees: NVIDIA Corporation - Applicants: NVIDIA Corporation - Inventors: Jonah M. Alben; William J. Dally - Web page: https://patentgrep.com/patent/US8786345B2 ## CPC - H03K 3/286: bistable - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - H03K 3/356139: {with synchronous operation} - H03K 3/356191: {with synchronous operation} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract One embodiment of the present invention sets forth a technique for capturing and storing a level of an input signal using a single-trigger low-energy flip-flop circuit that is fully-static and insensitive to fabrication process variations, The single-trigger low-energy flip-flop circuit presents only three transistor gate loads to the clock signal and none of the internal nodes toggle when the input signal remains constant, The output signal Q is set or reset at the rising clock edge using a single- trigger sub-circuit. A set or reset may be armed while the clock signal is low, and the set or reset is triggered at the rising edge of the clock. ## Claims ### Claim 1 A single-trigger low-energy flip-flop circuit, comprising: a trigger sub-circuit that includes a first clock-activated transistor that is directly coupled to power and is configured to arm a trigger signal when an input signal to the single-trigger low-energy flip-flop circuit is at a different level than a level of an output signal generated by the single-trigger low-energy flip-flop circuit, wherein the trigger sub-circuit comprises transistors configured to function as an exclusive-or gate with the input signal and the output signal as inputs and the trigger signal as an output; and a latch sub-circuit that includes a second clock-activated transistor and is configured to change the level of the output signal when the trigger signal is armed and a clock signal transitions from a first level to a second level and maintain the level of the output signal when the trigger signal is unarmed, wherein a gate of the first clock-activated transistor and a gate of the second clock-activated transistor are directly coupled to the clock signal. ### Claim 2 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, wherein the latch sub-circuit further comprises a third clock-activated transistor that is configured as a pull-up transistor. ### Claim 3 (depends on 2) The single-trigger low-energy flip-flop circuit of claim 2, wherein the third clock-activated transistor is enabled for every Nth clock cycle and N is greater than ten. ### Claim 4 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, wherein the trigger sub-circuit is configured to disarm the trigger signal when the output signal changes to be at the same level as the input signal and the clock signal is at the second level. ### Claim 5 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, wherein the trigger sub-circuit comprises an inverter and a transistor configured to function as a keeper circuit to maintain the trigger signal as unarmed if the input signal changes while the clock is at the second level. ### Claim 6 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, wherein the first clock-enabled transistor is configured as a pull-up transistor to enable the trigger sub-circuit when the clock is at the first level. ### Claim 7 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, further comprising an output inverter that is configured to isolate the output signal from a storage feedback loop within the latch sub-circuit. ### Claim 8 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, wherein a third clock-activated transistor is configured as a pull-up transistor to enable the latch sub-circuit when the clock signal is at the first level. ### Claim 9 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, wherein the second clock-activated transistor is configured as a pull-down transistor to enable the latch sub-circuit when the clock signal is at the second level. ### Claim 10 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, wherein the latch sub-circuit comprises transistors coupled in series between the power and a node and configured to pull-up the node, causing the output signal to remain unchanged when the input signal and the output signal are at the same level. ### Claim 11 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, wherein operation of the trigger sub-circuit and the latch sub-circuit does not depend on sizing relationships between transistors. ### Claim 12 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, wherein the trigger sub-circuit receives a feedback signal that is generated by the latch sub-circuit and configured to disarm the trigger signal. ### Claim 13 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, wherein the latch sub-circuit comprises a first inverter and a second inverter, and an output of the first inverter is coupled to an input of the second inverter and an output of the second inverter is coupled to an input of the first inverter. ### Claim 14 (depends on 13) The single-trigger low-energy flip-flop circuit of claim 13, wherein the first inverter and the second inverter form a storage sub-circuit of the latch sub-circuit. ### Claim 15 (depends on 1) The single-trigger low-energy flip-flop circuit of claim 1, wherein only three transistor gate loads are presented to the clock signal. ### Claim 16 A single-trigger low-energy flip-flop circuit, comprising: a trigger sub-circuit that includes a first dock-activated transistor and is configured to arm a trigger signal when an input signal to the single-trigger low-energy flip-flop circuit is at a different level than a level of an output signal generated by the single-trigger low-energy flip-flop circuit, wherein the trigger sub-circuit comprises transistors configured to function as an exclusive-or gate with the input signal and the output signal as inputs and the trigger signal as an output; and a latch sub-circuit that includes a second clock-activated transistor that is directly coupled to ground and is configured to change the level of the output signal when the trigger signal is armed and a clock signal transitions from a first level to a second level and maintain the level of the output signal when the trigger signal is unarmed. ### Claim 17 (depends on 16) The single-trigger low-energy flip-flop circuit of claim 16, wherein a gate of the first clock-activated transistor and a gate of the second clock-activated transistor are directly coupled to the clock signal.