# US 8,786,341 B1 · Frequency synthesizer with hit-less transitions between frequency- and phase-locked modes

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- Number: US 8,786,341 B1
- Document ID: US8786341B1
- Status: Granted
- Kind: B1
- Application number: 13/833,360
- Filed: 2013-03-15
- Granted: 2014-07-22
- Earliest claimed: 2013-03-15
- Assignees: Silicon Laboratories Inc.
- Applicants: Silicon Laboratories Inc.
- Inventors: Colin Weltin-Wu; Yunteng Huang
- Web page: https://patentgrep.com/patent/US8786341B1

## CPC

- H03L 7/1972: {for reducing the locking time interval (H03L7/1974, H03L7/199 take precedence)}
- H03L 7/1075: {by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence)}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A digital frequency synthesizer provides absolute phase lock and shorter settling time through the use of a digital filter with a phase and frequency path. Control logic control disables the frequency path during the frequency acquisition and sets a wide bandwidth. After frequency acquisition, a counter with digital phase information is reset using the input clock signal to bring the output phase closer to lock with the input signal and the control logic enables the phase path in the digital loop filter to achieve phase lock with a narrower bandwidth than the initial bandwidth.

## Claims

### Claim 1

An apparatus to lock an oscillator output signal to an input clock signal comprising:
a digital loop filter including a frequency path and a phase path, wherein the phase path is disabled during a portion of a start-up sequence;
an oscillator supplying the oscillator output signal; and
a counter coupled to the oscillator to count transitions of the oscillator output signal and coupled to the digital loop filter, the counter to supply a divided clock signal based on the oscillator output signal.

### Claim 2 (depends on 1)

The apparatus as recited in claim 1 further comprising:
a time-to-digital converter circuit, coupled the oscillator output signal and to the digital loop filter, to supply a quantized value of a phase of the oscillator output signal; and
a sampler circuit coupled to sample the quantized value according to the input clock signal to provide phase information indicative of a phase difference between the input clock signal and the oscillator output signal to the digital loop filter.

### Claim 3 (depends on 2)

The apparatus as recited in claim 2 further comprising:
a differentiator in the frequency path of the digital loop filter and wherein during startup, sampled count values from the counter are combined with the phase information and supplied to the differentiator to provide a quantized frequency measurement used to achieve frequency lock between the input signal and the oscillator output signal.

### Claim 4 (depends on 1)

The apparatus as recited in claim 1 wherein the counter is reset as part of a transition from a frequency-locked mode of operation to a phase-locked mode of operation to align the counter with the input clock signal.

### Claim 5 (depends on 1)

The apparatus as recited in claim 1 further comprising:
control logic to control the start-up sequence and transition from frequency-locked mode to phase-locked mode of operation.

### Claim 6 (depends on 5)

The apparatus as recited in claim 5 wherein the control logic during frequency acquisition is configured to cause the digital loop filter to utilize a first loop bandwidth for a first time period, and a second loop bandwidth, lower than the first loop bandwidth, for a second time period.

### Claim 7 (depends on 5)

The apparatus as recited in claim 5 wherein the control logic is configured to enable the phase path of the digital loop filter and to hold registers of the digital loop filter for at least one clock cycle in conjunction with the counter being reset as part of the transition.

### Claim 8 (depends on 1)

The apparatus as recited in claim 1 wherein an output signal is supplied from the counter.

### Claim 9 (depends on 1)

The apparatus as recited in claim 1 wherein information from the phase path and information from the frequency path are combined on enabling of the phase path to generate a digital control word to control the oscillator.

### Claim 10 (depends on 1)

The apparatus as recited in claim 1 wherein the frequency path comprises:
a differentiator coupled to receive phase and frequency information as a differentiator input signal generated by the counter and a time-to-digital converter circuit and to supply a differentiator output signal;
a first summing circuit coupled to receive the differentiator output signal and a frequency target value;
a gain circuit coupled to the first summing circuit;
a second summing circuit coupled to receive a value from the phase path that does not affect the digital control word when the phase path is disabled;
a gear shift circuit to adjust bandwidth; and
an integrator coupled to the gear shift circuit to supply the digital control word.

### Claim 11 (depends on 10)

The apparatus as recited in claim 10 wherein the phase path comprises:
a third summing circuit coupled to receive low order bits of the differentiator input signal and a phase target value;
the second summing circuit coupled to receive output from the third summing circuit when the phase path is enabled;
the gear shift circuit; and
the integrator.

### Claim 12

A method of locking an oscillator output signal to an input clock signal comprising:
generating the oscillator output signal from an oscillator;
supplying a digital control word to control the oscillator from a digital loop filter;
generating a count value in a ripple counter coupled to the oscillator, the count value being based on the oscillator output signal;
generating a digital representation of a phase difference between the input clock signal and the oscillator output signal;
adjusting the digital control word from the digital loop filter according to the count value of the ripple counter and the phase difference; and
disabling a phase path of the digital loop filter while operating a frequency path of the digital loop filter during frequency acquisition.

### Claim 13 (depends on 12)

The method as recited in claim 12 further comprising resetting the ripple counter to align the ripple counter to the input clock signal after a predetermined time of frequency acquisition.

### Claim 14 (depends on 12)

The method as recited in claim 12 further comprising:
during the frequency acquisition operating the digital loop filter with a first bandwidth for a first time period, and operating the digital loop filter with a second bandwidth lower than the first bandwidth for a second time period during another portion of the frequency acquisition.

### Claim 15 (depends on 12)

The method as recited in claim 12 further comprising:
after a predetermined time period, transitioning from a frequency-locked mode of operation to a phase-locked mode of operation, the transitioning including enabling the phase path of the digital loop filter and resetting the ripple counter.

### Claim 16 (depends on 15)

The method as recited in claim 15 further comprising blocking clocking registers of the digital loop filter for one or more cycles in conjunction with resetting the ripple counter and turning on the phase path to avoid a discontinuity in the frequency path.

### Claim 17 (depends on 14)

The method as recited in claim 14 further comprising combining information from the phase path and information from the frequency path after enabling of the phase path, to generate the digital control word.

### Claim 18 (depends on 14)

The method as recited in claim 14 further comprising differentiating information supplied to the frequency path during the frequency acquisition to generate frequency information.

### Claim 19

A method of locking an oscillator output signal to an input clock signal comprising:
generating the oscillator output signal from an oscillator;
supplying a digital control word to control the oscillator from a digital loop filter;
in response to a startup condition enabling a frequency path of the digital loop filter and disabling a phase path while achieving frequency lock; and
transitioning between a frequency-locked mode and a phase-locked mode of operation, the transitioning including enabling the phase path, resetting a counter coupled to the oscillator and the digital loop filter, and holding registers in the digital loop filter for at least clock cycle.

### Claim 20 (depends on 19)

The method as recited in claim 19 further comprising:
generating count values in the counter coupled to the oscillator, the count value being based on the oscillator output signal;
generating digital phase information corresponding to a phase difference between the input clock signal and the oscillator output signal; and
supplying the count values and the phase information to the digital loop filter.