# US 8,786,339 B2 · Apparatuses and methods for delaying signals using a delay line with homogenous architecture and integrated measure initialization circuitry

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- Number: US 8,786,339 B2
- Document ID: US8786339B2
- Status: Granted
- Kind: B2
- Application number: 13/692,666
- Filed: 2012-12-03
- Published: 2014-06-05
- Granted: 2014-07-22
- Earliest claimed: 2012-12-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Yantao Ma
- Web page: https://patentgrep.com/patent/US8786339B2

## CPC

- H03L 7/0814: {the phase shifting device being digitally controlled}
- H03H 11/26: Time-delay networks
- H03K 5/133: using a chain of active delay devices
- H03L 7/08: Details of the phase-locked loop
- H03L 7/0816: {the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- H03K 2005/00058: {controlled by a digital setting}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03H: IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS (waveguides, resonators, lines or other devices of the waveguide type H01P)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Apparatuses and methods for delaying signals using a delay line are described. An example apparatus includes a controller configured to in a first mode, set a delay length, and, in a second mode, to determine an initial delay. The apparatus further including a delay line circuit coupled to the controller and includes delay elements. Each of the delay elements includes delay gates that are the same type of delay gate. The delay line circuit is configured to, in the first mode propagate a signal through one or more of the delay elements to provide a delayed signal. The delay line circuit is further configured to, in the second mode, propagate a pulse signal through one or more of the delay elements and provide a corresponding output signal from each of the one or more delay elements responsive to the pulse signal reaching an output of the corresponding delay element.

## Claims

### Claim 1

An apparatus comprising:
a controller configured to:
in a first mode, set a delay length; and
in a second mode, determine an initial delay; and
a delay line circuit coupled to the controller, the delay line circuit including a plurality of delay elements, wherein each of the plurality of delay elements includes two or more delay gates that are the same type of delay gate, the delay line circuit configured to:
in the first mode, propagate a signal through one or more of the plurality of delay elements to provide a delayed signal at an output; and
in the second mode, propagate a pulse signal through one or more of the plurality of delay elements and provide a corresponding output signal from each of the one or more of the plurality of delay elements responsive to the pulse signal reaching an output of the corresponding delay element.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein, in the first mode, the plurality of delay elements are configured to propagate the signal through the one or more of the plurality of delay elements along a signal path to provide the delayed signal.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the signal path begins at a first delay element of the plurality of delay elements and loops back through the first delay element.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein signal path loops back at a return delay element of the plurality of delay elements.

### Claim 5 (depends on 2)

The apparatus of claim 2, wherein the signal path is a first signal path, and in the first mode, the plurality of delay elements are further configured to contemporaneously propagate the signal along a second signal path to provide a second delayed signal, wherein the second signal path includes at least one of the plurality of delay elements.

### Claim 6 (depends on 2)

The apparatus of claim 2, wherein the first signal path is different from the second signal path.

### Claim 7 (depends on 5)

The apparatus of claim 5, wherein the first signal path includes a first number of delay elements of the plurality of delay elements and the second signal path includes a second number of delay elements of the plurality of delay elements, wherein the first number of delay elements is different than the second number of delay elements.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the first number is an even number of delay elements of the plurality of delay elements and wherein the second number is an odd number of delay elements of the plurality of delay element.

### Claim 9 (depends on 1)

The apparatus of claim 1, wherein, in the second mode, the plurality of delay elements are configured to propagate the pulse signal through the one or more of the plurality of delay elements along a signal path sequentially through each of the one or more of the plurality of delay elements.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the signal path includes at least two delay gates from each of the one or more of the plurality of delay elements.

### Claim 11

A method, comprising:
configuring a delay line circuit of a delay-locked loop to a first configuration during a first mode;
in the first mode:
propagating a signal along a first signal path through one or more of a plurality of delay elements of the delay line circuit, wherein each of the plurality of delay elements includes a corresponding two or more delay gates, wherein each of the two or more delay gates are the same type of delay gate; and
providing a delayed signal from the delay line circuit;
configuring the delay line circuit to a second configuration during a second mode; and
in the second mode:
propagating a pulse signal along a second signal path through one or more of the plurality of delay elements;
providing a corresponding asserted output signal from one or more of the plurality of delay elements responsive to the pulse signal reaching an output of the corresponding delay element; and
determining an initial delay based on a the asserted output signals.

### Claim 12 (depends on 11)

The method of claim 11, wherein, the signal path forms a loop starting at an input of a first delay element of the one or more of the plurality of delay elements and ending at an output of the first delay element.

### Claim 13 (depends on 12)

The method of claim 12, further comprising, in the first mode, adjusting the delay length to adjust a delay of the delayed signal relative to the signal.

### Claim 14 (depends on 11)

The method of claim 11, further comprising, in the second mode, setting a value in a shift register corresponding to the initial delay.

### Claim 15 (depends on 11)

The method of claim 11, wherein, in the second mode, determining the initial delay comprises counting a number of asserted output signals.

### Claim 16 (depends on 11)

The method of claim 11, wherein, in the second mode, determining the initial delay comprises determining a particular delay element associated with the asserted output signal that was received last.

### Claim 17

A method, comprising:
configuring a first delay element and a second delay element to a first configuration during a first mode;
in the first mode:
receiving a signal at a first delay gate the first delay element;
providing the signal from the first delay gate of the first delay element through a first delay gate and a second delay gate of the second delay element to a second delay gate of the first delay element; and
outputting a delayed signal from the second delay gate of the first delay element based on the signal received at the second delay gate of the first delay element, wherein the first delay gate and the second delay gate of the first delay element and the first delay gate and the second delay gate of the second delay element include a same delay gate type;
configuring the first delay element and the second delay element to operate in a second mode based on the control signals having a second configuration; and
in the second mode:
providing a pulse signal from a third delay gate of the first delay element to a fourth delay gate of the first delay element and to a third delay gate of a second delay element;
outputting a first output signal from the fourth delay gate of the first delay element to a controller and to the third delay gate of the second delay element; and
outputting a second output signal from the fourth delay gate of the second delay element to the controller, wherein the controller determines an initial delay based on the first output signal and the second output signal.

### Claim 18 (depends on 17)

The method of claim 17, wherein the first delay gate, the second delay gate, the third delay gate, and the fourth delay gate of the first delay element are each two-input NAND gates, and wherein the first delay gate, the second delay gate, the third delay gate, and the fourth delay gate of the second delay element are each two-input NAND gates.

### Claim 19 (depends on 17)

The method of claim 17, further comprising, in the second mode, receiving the pulse signal at the third delay gate of the first delay element.

### Claim 20 (depends on 17)

The method of claim 17, further comprising exiting the second mode responsive to setting the initial delay.