# US 8,786,337 B2 · Low jitter clock generator for multiple lanes high speed data transmitter

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- Number: US 8,786,337 B2
- Document ID: US8786337B2
- Status: Granted
- Kind: B2
- Application number: 13/829,759
- Filed: 2013-03-14
- Published: 2013-11-14
- Granted: 2014-07-22
- Earliest claimed: 2012-05-14
- Assignees: Ensphere Solutions, Inc.
- Applicants: Ensphere Solutions, Inc.
- Inventors: Hessam Mohajeri; Bruno Tourette
- Web page: https://patentgrep.com/patent/US8786337B2

## CPC

- H03L 7/0814: {the phase shifting device being digitally controlled}
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- H03L 7/1075: {by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence)}
- H03L 7/1976: {using a phase accumulator for controlling the counter or frequency divider}
- H03L 7/235: {Nested phase locked loops}
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

The present disclosure provides a clock generator circuit comprising a master clock generator unit configured to generate a master clock signal, and a plurality of slave phase locked loop units. Each of the plurality of slave phase looked loop units is configured to receive the master clock signal as an input reference signal and a corresponding source clock signal. The slave phase locked loop unit may comprise an inner loop and an outer loop. The inner loop may comprise a frequency synthesizer locked on a master clock signal received from a master clock generator unit, while the outer loop may comprise a binary phase detector, an output of which goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

## Claims

### Claim 1

A clock generator circuit comprising:
a master clock generator unit configured to generate a master clock signal; and
a plurality of slave phase locked loop units, each configured to receive the master clock signal as an input reference signal and a corresponding source clock signal,
wherein:
each of the plurality of slave phase locked loop units is a dual loop slave phase lock loop unit that comprises an inner loop and an outer loop, and
the inner loop comprises a frequency synthesizer locked on the master clock signal received from the master clock generator unit.

### Claim 2 (depends on 1)

The clock generator circuit of claim 1, wherein the master clock generator unit is a master phase locked loop.

### Claim 3 (depends on 1)

The clock generator circuit of claim 1, wherein the master clock generator unit is an LC based oscillator.

### Claim 4 (depends on 1)

The clock generator circuit of claim 1, wherein each of the plurality of slave phase locked loop units is fully digital or the phase locked loop is fully digital except the inner loop ring oscillator, charge pump and low-pass filter.

### Claim 5 (depends on 1)

The clock generator circuit of claim 1, wherein the plurality of slave phase locked loop units do not comprise any low noise phase locked loops.

### Claim 6 (depends on 5)

The clock generator circuit of claim 5, wherein each of the slave phase locked loop units comprises a fractional N synthesizer sub-circuit based on a digital phase rotator.

### Claim 7 (depends on 1)

The clock generator circuit of claim 1, wherein the frequency synthesizer comprises a sigma delta fractional N synthesizer and a feedback phase rotator.

### Claim 8 (depends on 1)

The clock generator circuit of claim 1, wherein the outer loop controls frequency programming of the inner loop while locking on the corresponding source clock signal.

### Claim 9 (depends on 1)

The clock generator circuit of claim 1, wherein the outer loop is fully digital.

### Claim 10 (depends on 1)

The clock generator circuit of claim 1, wherein the outer loop has a bandwidth adjustable to depend on the jitter transfer requirements of the system to filter out the jitter from the corresponding source clock signal.

### Claim 11 (depends on 1)

The clock generator circuit of claim 1, wherein the outer loop comprises a binary phase detector.

### Claim 12 (depends on 11)

The clock generator circuit of claim 11, wherein the binary phase detector comprises a single flip flop.

### Claim 13 (depends on 11)

The clock generator circuit of claim 11, wherein output of the binary phase detector goes to a loop filter with proportional and integral action, controlling the inner loop frequency value via a sigma delta input.

### Claim 14 (depends on 11)

The clock generator circuit of claim 11, wherein a second phase rotator followed by a divider connects an inner loop output and a binary phase detector input.

### Claim 15 (depends on 11)

The clock generator circuit of claim 11, wherein the clock generator is implemented using high density deep sub micron CMOS process technology.