# US 8,786,336 B1 · Phase-lock loop-based clocking system, methods and apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,336 B1 - Document ID: US8786336B1 - Status: Granted - Kind: B1 - Application number: 14/046,462 - Filed: 2013-10-04 - Granted: 2014-07-22 - Earliest claimed: 2011-10-28 - Assignees: LightLab Imaging, Inc. - Applicants: Joseph M. Schmitt - Inventors: Joseph M. Schmitt - Web page: https://patentgrep.com/patent/US8786336B1 ## CPC - H03L 7/104: {using an additional signal from outside the loop for setting or controlling a parameter in the loop (H03L7/107, H03L7/12 take precedence)} - H03L 7/07: using several loops, e.g. for redundant clock signal generation - H03L 7/0805: {the loop being adapted to provide an additional control signal for use outside the loop} - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) ## Abstract In part, the invention relates to an optical coherence tomography system that includes one or more phased-locked loop circuits. In one embodiment, the phased-locked loop circuit includes a phase detector, a loop filter, and a voltage controlled oscillator wherein the phased-locked loop circuit is configured to generate a sample clock. The optical coherence tomography system can include an analog to digital converter having a sample clock input, an interferometric signal input, and a sample data output, the analog to digital converter configured to receive the sample clock and sample OCT data in response thereto. In one embodiment, the phased-locked loop circuit is configured to lock on a first signal in less than or equal to about 1 microseconds. ## Claims ### Claim 1 A clocking system comprising: a zero-crossing detector having a first input and a first output, the first input configured to receive a first input signal; and a phased-locked loop circuit having a second input and a second output, wherein the second input is in electrical communication with the first output, the circuit comprising: a phase detector in electrical communication with the second input, the phase detector comprising a reference input and a phase error signal output; and a voltage controlled oscillator (VCO), the voltage controlled oscillator having a VCO frequency; and a phase error compensator circuit in electrical communication with the phase error signal output and comprising a phase error compensator output and a sweep trigger signal input, wherein the VCO is in electrical communication with the phase error compensator output and the second output, and wherein the phase-locked loop circuit is configured to generate a clock signal. ### Claim 2 A method of generating a clock signal comprising: receiving a first clock signal having a first phase at a first input to a phase-locked loop; locking on the first clock signal within a first time period; detecting the first phase of the first clock signal; and frequency multiplying the first clock signal or a signal derived therefrom by N using an oscillator to generate a clock signal. ### Claim 3 (depends on 2) The method of claim 2 wherein N is a positive integer that ranges from 1 to 16. ### Claim 4 (depends on 1) The clocking system of claim 1 wherein the phase-locked loop circuit further comprises a divide by N circuit having a divide by N input in communication with the second output and a divide by N circuit output in electrical communication with the reference input. ### Claim 5 (depends on 1) The clocking system of claim 1 wherein the phase error compensator further comprises: a first phase error compensator memory; a digital to analog converter comprising a digital to analog trigger input in communication with the sweep trigger input and a memory input in communication with the first phase error compensator memory and an analog output that comprises the phase compensator output; a second phase error compensator memory; an analog to digital converter having an analog input in electrical communication with the phase error signal output, an analog to digital trigger input in communication with the sweep trigger input, and a analog to digital output in electrical communication with the second phase error compensator memory. ### Claim 6 (depends on 1) The clocking system of claim 1 further comprising: an analog to digital converter having a sample clock input, an interferometric signal input, and a sample data output, the analog to digital converter configured to receive the sample clock and sample OCT data in response thereto. ### Claim 7 (depends on 1) The clocking system of claim 1 wherein the phased-locked loop circuit is configured to lock on a first signal received at the second input in less than or equal to about 1 microseconds. ### Claim 8 (depends on 1) The clocking system of claim 1 wherein further comprising a loop filter in electrical communication with the VCO and wherein the first input signal has a frequency and a mean frequency and wherein the loop filter comprises a first diode and a second diode configured to automatically block current flow during a first frequency state. ### Claim 9 (depends on 1) The clocking system of claim 1 wherein the phase-locked loop circuit is configured to transmit or lock on frequencies greater than or equal to about 20 MHz. ### Claim 10 (depends on 1) The clocking system of claim 1 wherein the voltage controlled oscillator has a response time less than about 100 nanoseconds. ### Claim 11 (depends on 2) The method of claim 2 further comprising sampling optical coherence tomography data using an analog to digital converter; and clocking the analog to digital converter using the clock signal. ### Claim 12 (depends on 2) The method of claim 2 further comprising compensating for feedthrough noise by filtering the first clock signal using a loop filter comprising a RLC or RC circuit. ### Claim 13 (depends on 2) The method of claim 2 further comprising clocking an analog to digital converter in electrical communication with a photoreceiver in optical communication with an interferometer configured to collect coherence tomography data. ### Claim 14 (depends on 2) The method of claim 2 further comprising compensating wherein the first time period is less than or equal to about 1 microseconds. ### Claim 15 (depends on 2) The method of claim 2 further comprising the steps of filtering the first clock signal using a loop filter having a control signal input. ### Claim 16 A clocking system comprising: a zero-crossing detector having a first input and a first output, the first input configured to receive a first input signal; and a phased-locked loop circuit having a second input and a second output, wherein the second input is in electrical communication with the first output, the phase-locked loop circuit comprising: a phase detector in electrical communication with the second input, the phase detector comprising a reference input and a phase error signal output, and a voltage controlled oscillator (VCO), the voltage controlled oscillator having a VCO frequency; and an arbitrary waveform generator comprising an arbitrary waveform generator output and a sweep trigger signal input, wherein the VCO is in electrical communication with the arbitrary waveform generator output and a phase error signal output through a loop filter and wherein the phase-locked loop circuit is configured to generate a clock signal. ### Claim 17 (depends on 16) The clocking system of claim 16 wherein the arbitrary waveform generator comprises a digital to analog converter in electrical communication with a memory and having a digital to analog converter output out comprising the arbitrary waveform generator output. ### Claim 18 (depends on 16) The clocking system of claim 16 wherein the phase-locked loop circuit is configured to transmit or lock on frequencies greater than or equal to about 20 MHz. ### Claim 19 (depends on 16) The clocking system of claim 16 wherein the voltage controlled oscillator has a response time less than about 100 nanoseconds. ### Claim 20 (depends on 16) The clocking system of claim 16 further comprising a loop filter in electrical communication with the VCO, wherein the loop filter comprises an RLC circuit or a RC circuit.