# US 8,786,331 B2 · System for reducing noise in a chemical sensor array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,331 B2 - Document ID: US8786331B2 - Status: Granted - Kind: B2 - Application number: 13/801,709 - Filed: 2013-03-13 - Published: 2013-12-05 - Granted: 2014-07-22 - Earliest claimed: 2012-05-29 - Assignees: Life Technologies Corporation - Applicants: Life Technologies Corporation - Inventors: Jeremy Jordan; Todd Rearick - Web page: https://patentgrep.com/patent/US8786331B2 ## CPC - H03K 17/162: {without feedback from the output circuit to the control circuit} - G01N 27/4145: {specially adapted for biomolecules, e.g. gate electrode with immobilised receptors} - G06F 1/06: Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - H03K 19/00346: {Modifications for eliminating interference or parasitic voltages or currents} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G01N: INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES (measuring or testing apparatus or processes other than immunoassay, involving enzymes or microorganisms C12M, C12Q) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A system including a power supply and a clock circuitry to generate a plurality of clock signals. Each clock signal is synchronous with a primary clock signal. First, second, and third clock signals of the plurality of clock signals are asynchronous to each other. The system further includes a plurality of switches. Each switch of the plurality of switches is communicatively coupled to the power supply and the clock circuitry. A first switch of the plurality of switches receives the first clock signal, a second switch of the plurality of switches receives the second clock signal, and a third switch of the plurality of switches receives the third clock signal. ## Claims ### Claim 1 A system comprising: a first analog-to-digital converter to receive an output signal from a sensor array; a first switcher to power the sensor array and the first analog-to-digital converter; and a clock generator to generate a plurality of clock signals that are synchronous with a primary clock signal, the clock generator provides a first clock signal of the plurality to the first analog-to-digital converter and provides a second clock signal of the plurality to the first switcher, the first clock signal is asynchronous with the second clock signal. ### Claim 2 (depends on 1) The system of claim 1, wherein a sensor in the sensor array is at least one of a chemically-sensitive field effect transistor (chemFET) and an ion-sensitive field effect transistor (ISFET). ### Claim 3 (depends on 2) The system of claim 2, wherein the chemFET/ISFET detects a chemical reaction occurring proximate to the chemFET/ISFET. ### Claim 4 (depends on 1) The system of claim 1, wherein the sensor array includes an output circuit to receive output signals from the sensor array. ### Claim 5 (depends on 4) The system of claim 4, wherein the sensor array includes an output circuit to provide the output signals to the first analog-to-digital converter. ### Claim 6 (depends on 1) The system of claim 1, wherein the system further includes a second switcher responsive to a third clock signal that is asynchronous with the first clock signal such that a power consumption on a power supply from the second switcher is staggered. ### Claim 7 (depends on 1) The system of claim 1, wherein the system further includes a second switcher responsive to a third clock signal having a rising edge that is concurrent with a falling edge of the first clock signal. ### Claim 8 (depends on 1) The system of claim 1, wherein the first and second switchers are disposed on a same substrate. ### Claim 9 (depends on 1) The system of claim 1, wherein the analog-to-digital converter and the sensor array are disposed on a same substrate. ### Claim 10 (depends on 1) The system of claim 1, wherein the analog-to-digital converter is disposed on a first substrate and the sensor array is disposed on a second substrate. ### Claim 11 (depends on 1) The system of claim 1, wherein a power supply provides power to a first switcher on a first substrate and provides power to a second switcher on a second substrate. ### Claim 12 A system comprising: a first analog-to-digital converter to receive an output signal from a sensor array; a first switcher to power the sensor array and the first analog-to-digital converter; and a clock generator to generate a plurality of clock signals that are synchronous with a primary clock signal, the clock generator provides a first clock signal of the plurality to the first analog-to-digital converter and provides a second clock signal of the plurality to the first switcher, the first clock signal is asynchronous with the second clock signal, wherein a power supply provides power to a first switcher on a first substrate and the first switcher provides power to a second switcher on a second substrate.