# US 8,786,330 B1 · System and method for a frequency doubler > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,330 B1 - Document ID: US8786330B1 - Status: Granted - Kind: B1 - Application number: 13/797,187 - Filed: 2013-03-12 - Granted: 2014-07-22 - Earliest claimed: 2013-03-12 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Abhiram Chakraborty; Saverio Trotta - Web page: https://patentgrep.com/patent/US8786330B1 ## CPC - H03B 19/14: by means of a semiconductor device - H03B: GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS (generators adapted for electrophonic musical instruments G10H; masers or lasers H01S; generation of oscillations in plasma H05H) ## Abstract In accordance with an embodiment, a frequency doubling circuit includes a differential transistor pair coupled to an input port of the frequency doubling circuit, a first differential cascode stage having an input coupled to an output of the differential transistor pair, a plurality of first impedance elements coupled between the output of the differential transistor pair and the input of the first differential cascode stage, and an output combining network coupled between the first differential cascode stage and an output port of the frequency doubling circuit. ## Claims ### Claim 1 A frequency doubling circuit comprising: a differential transistor pair coupled to an input port of the frequency doubling circuit; a first differential cascode stage having an input coupled to an output of the differential transistor pair; a plurality of first impedance elements coupled between the output of the differential transistor pair and the input of the first differential cascode stage; and an output combining network coupled between the first differential cascode stage and an output port of the frequency doubling circuit. ### Claim 2 (depends on 1) The frequency doubling circuit of claim 1, wherein: the differential transistor pair comprises a first plurality of bipolar junction (BJT) transistors; and the first differential cascode stage comprises a second plurality of BJTs. ### Claim 3 (depends on 1) The frequency doubling circuit of claim 1, wherein the plurality of first impedance elements comprises transmission line elements. ### Claim 4 (depends on 1) The frequency doubling circuit of claim 1, therein the plurality of first impedance elements comprise inductors. ### Claim 5 (depends on 1) The frequency doubling circuit of claim 1, wherein the plurality of first impedance elements is configured to provide an impedance match between the output of the differential transistor pair and the input of the first differential cascode stage. ### Claim 6 (depends on 1) The frequency doubling circuit of claim 1, wherein the frequency doubling circuit is configured to operate at an input frequency of greater than 30 GHz. ### Claim 7 (depends on 1) The frequency doubling circuit of claim 1, wherein the output combining network comprises: a plurality of second impedance elements coupled between the output of the first differential cascode stage and a common node; and an output matching network coupled between the common node and the output port of the frequency doubling circuit. ### Claim 8 (depends on 7) The frequency doubling circuit of claim 7, wherein the plurality of second impedance elements and the output matching network comprises transmission line elements. ### Claim 9 (depends on 1) The frequency doubling circuit of claim 1, wherein the differential transistor pair, the first differential cascode stage, the plurality of first impedance element and the output combining network are disposed in an integrated circuit. ### Claim 10 (depends on 1) The frequency doubling circuit of claim 1, further comprising: a second differential cascode stage having an input coupled to an output of the first differential cascode stage; and a plurality of third impedance elements coupled between the output of the first differential cascode stage and the input of the second differential cascode stage. ### Claim 11 A semiconductor circuit comprising: an input stage comprising a first transistor and a second transistor, wherein bases of the first transistor and the second transistor are coupled to an input port, and an emitter of the first transistor is coupled to an emitter of the second transistor; a cascode stage comprising a third transistor and a fourth transistor; a first transmission line element coupled between a collector of the first transistor and an emitter of the third transistor; a second transmission line element coupled between a collector of the second transistor and an emitter of the fourth transistor; and an output stage having a first input coupled to a collector of the third transistor, a second input coupled to a collector of the fourth transistor, and an output coupled to an output port. ### Claim 12 (depends on 11) The circuit of claim 11, wherein the output stage comprises: a third transmission line element coupled between the collector of the third transistor and a common node; a fourth transmission line element coupled between the collector of the fourth transistor and the common node; and a matching network comprising at least one transmission line coupled between the common node and the output port of the circuit. ### Claim 13 (depends on 12) The circuit of claim 12, further comprising a first quarter wave transmission line coupled between the common node and a power supply node, wherein the first quarter wave transmission line is configured to have a quarter wave frequency of about twice an input frequency of the circuit at the input port. ### Claim 14 (depends on 11) The circuit of claim 11, further comprising a second quarter wave transmission line coupled between the emitters of the first and second transistors and a supply reference node. ### Claim 15 (depends on 14) The circuit of claim 14, wherein the supply reference node comprises a ground node. ### Claim 16 (depends on 11) The circuit of claim 11, wherein the input port is configured to be coupled to a driving stage. ### Claim 17 (depends on 11) The circuit of claim 11, wherein the output port is configured to provide an output signal having a frequency that is twice a frequency of a signal at the input port. ### Claim 18 (depends on 17) The circuit of claim 17, wherein the frequency of the signal at the input is greater than 30 GHz. ### Claim 19 A method of doubling a frequency, the method comprising: providing a first signal having a first frequency to an input port of a frequency doubling circuit comprising a differential transistor pair coupled to an input port of the frequency doubling circuit, a differential cascode stage having an input coupled to an output of the differential transistor pair, a plurality of first transmission line elements coupled between the output of the differential transistor pair and the input of the differential cascode stage, and an output combining network coupled between the differential cascode stage and an output port of the frequency doubling; and receiving a second signal from the output port of the frequency doubling circuit, the second signal having a second frequency that is twice the first frequency. ### Claim 20 (depends on 19) The method of claim 19, wherein the first frequency is greater than 30 GHz. ### Claim 21 (depends on 19) The method of claim 19, wherein providing a first signal comprises providing the first signal to an integrated circuit comprising the frequency doubling circuit. ### Claim 22 (depends on 19) The method of claim 19, wherein providing the first signal comprises providing the first signal from a local oscillator (LO) buffer.