# US 8,786,325 B2 · Integrated circuit chip and system having the same

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- Number: US 8,786,325 B2
- Document ID: US8786325B2
- Status: Granted
- Kind: B2
- Application number: 14/145,489
- Filed: 2013-12-31
- Published: 2014-04-24
- Granted: 2014-07-22
- Earliest claimed: 2011-10-25
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Seung-Min Oh
- Web page: https://patentgrep.com/patent/US8786325B2

## CPC

- G11C 7/1066: {Output synchronization}
- H03K 23/667: {by switching the base during a counting cycle}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

An integrated circuit chip includes: an internal circuit; a data output circuit configured to output a data packet of the internal circuit in response to a strobe signal; an oscillator configured to generate a first clock signal; a divider configured to divide the first clock signal and generate a second clock signal; and a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

## Claims

### Claim 1

An integrated circuit chip comprising:
an internal circuit;
an output circuit configured to output a data packet of the internal circuit in response to a strobe signal;
a first oscillator configured to generate a first clock signal;
a second oscillator configured to generate a second clock signal having a lower frequency than the first clock signal; and
a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.

### Claim 2 (depends on 1)

The integrated circuit chip of claim 1, wherein the strobe signal supply unit is configured to be turned on during the transmission of the data packet, and
the second oscillator is configured to be turned on during the initial period.

### Claim 3 (depends on 1)

The integrated circuit chip of claim 1, wherein the internal circuit is configured to generate an output enable signal indicating the transmission of the data packet, the integrated circuit chip further comprises an initial period signal generation unit configured to generate an initial period signal that is activated during an initial activation period of the output enable signal, and
the strobe signal supply unit is configured to supply the second clock signal as the strobe signal while the initial period signal is activated and supply the first clock signal as the strobe signal while the initial period signal is deactivated.

### Claim 4 (depends on 3)

The integrated circuit chip of claim 3, wherein the second oscillator is configured to be activated in response to the initial period signal.

### Claim 5 (depends on 3)

The integrated circuit chip of claim 3, wherein the strobe signal supply unit is configured to supply the strobe signal during the activation period of the output enable signal.

### Claim 6

A system comprising:
a first chip;
a second chip; and
a data channel between the first and second chips,
wherein the first chip comprises:
an internal circuit;
a data output circuit configured to output a data packet of the internal circuit to the data channel in response to a strobe signal;
a first oscillator configured to generate a first clock signal;
a second oscillator configured to generate a second clock signal having a lower frequency than the first clock signal; and
a strobe signal supply unit configured to supply the second clock signal as the strobe signal during an initial period of transmission of the data packet and supply the first clock signal as the strobe signal after the initial period.