Phase frequency detector
AssigneeMimos Berhad
InventorsMahmoud Hammamm Ismail Nesreen, Shahiman Mohd. Sulaiman Mohd
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Abstract
The present invention relates to a phase frequency detector (PFD) (100) for use as one of the blocks in a phase-locked loop. The PFD of the present invention has zero dead zone, has a simpler structure with a minimum number of transistors and requires a smaller area. The PFD of the present invention does not use any inverter or delay gate as found in the conventional PFD. Instead, the PFD of the present invention utilizes feedback transistors that save power and thus the PFD of the present invention is suitable to be used in low power applications.
Claims15
A phase frequency detector, comprising:
- (a) a first signal receiving means including a first input terminal to receive a first input signal and a second input terminal to receive a second input signal;
- (b) a second signal receiving means cross-coupled said first input terminal to receive said first input signal and said second input terminal to receive said second input signal;
- (c) a first node connected for charging or discharging depending on the signals received at said input terminals;
- (d) a second node connected for charging or discharging depending on the signals received at said input terminals;
- (e) a first control logic circuit for receiving a control signal output by said first node and output a first signal to an output terminal;
- and
- (f) a second control logic circuit for receiving a control signal output by said second node and output a second signal to an output terminal;
- (g) a first feedback means comprising a first feedback transistor for receiving signals from said output terminal of said second control logic circuit;
- (h) a second feedback means comprising a second feedback transistor for receiving signals from said output terminal of said first control logic circuit,
- wherein said phase frequency detector comprises no more than 12 transistors.
A method for generating a first output signal and a second output signal corresponding to phase difference or frequency difference between a first input signal and a second input signal, comprising:
- operating a phase frequency detector with feedback transistor and no more than 12 transistors, the phase frequency detector being configured for
- receiving at least two input signals, said first input signal and said second input signal,
- detecting an edge of said first input signal to generate said first output signal in response to said first input signal, and
- detecting an edge of said second input signal to generate said second output signal in response to said second input signal,
- wherein the pulse width difference between said first output signal and said second output signal represents the difference of said first and second input signals.
Dependencies are inferred from the claim text.