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US 8,786,313 B2Granted
Logic circuit and display device having the same
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorDaisuke Kawae
Life of this patent
Estimating the term…
Abstract
It is an object to provide a logic circuit which can be operated even when unipolar transistors are used. A logic circuit includes a source follower circuit and a logic circuit an input portion of which is connected to an output portion of the source follower circuit and all transistors are unipolar transistors. A potential of a wiring for supplying a low potential connected to the source follower circuit is lower than a potential of a wiring for supplying a low potential connected to the logic circuit which includes unipolar transistors. In this manner, a logic circuit which can be operated even with unipolar depletion transistors can be provided.
Claims37
A display device comprising:
- a pixel portion comprising a pixel transistor and a conductive line;
- and
- a driver circuit connected to the conductive line and comprising:
- a source follower circuit comprising a first input portion, an output portion, and a bias input portion;
- a logic circuit comprising a second input portion electrically connected to the output portion of the source follower circuit, the logic circuit comprising a driver transistor;
- a first wiring electrically connected to the source follower circuit, the first wiring being adapted to be supplied with a first constant low potential;
- a second wiring electrically connected to the logic circuit, the second wiring being adapted to be supplied with a second constant low potential;
- a third wiring electrically connected to the source follower circuit, the third wiring being adapted to be supplied with a first constant high potential;
- and
- a fourth wiring electrically connected to the logic circuit, the fourth wiring being adapted to be supplied with a second constant high potential,
- wherein the first constant low potential is lower than the second constant low potential.
8 more elements
A display device comprising:
- a pixel portion comprising an organic EL element, a pixel transistor, and a conductive line;
- and
- a driver circuit connected to the conductive line and comprising:
- a source follower circuit comprising a first input portion, an output portion, and a bias input portion;
- a logic circuit comprising a second input portion electrically connected to the output portion of the source follower circuit, the logic circuit comprising a driver transistor;
- a first wiring electrically connected to the source follower circuit, the first wiring being adapted to be supplied with a first constant low potential;
- a second wiring electrically connected to the logic circuit, the second wiring being adapted to be supplied with a second constant low potential;
- a third wiring electrically connected to the source follower circuit, the third wiring being adapted to be supplied with a first constant high potential;
- and
- a fourth wiring electrically connected to the logic circuit, the fourth wiring being adapted to be supplied with a second constant high potential,
- wherein the first constant low potential is lower than the second constant low potential, and
- wherein the driver transistor comprises silicon as a semiconductor.
9 more elements
A display device comprising:
- a pixel portion comprising a first substrate, a second substrate, a liquid crystal element between the first substrate and the second substrate, a pixel transistor, and a conductive line;
- and
- a driver circuit connected to the conductive line and comprising:
- a source follower circuit comprising a first input portion, an output portion, and a bias input portion;
- a logic circuit comprising a second input portion electrically connected to the output portion of the source follower circuit, the logic circuit comprising a driver transistor;
- a first wiring electrically connected to the source follower circuit, the first wiring being adapted to be supplied with a first constant low potential;
- a second wiring electrically connected to the logic circuit, the second wiring being adapted to be supplied with a second constant low potential;
- a third wiring electrically connected to the source follower circuit, the third wiring being adapted to be supplied with a first constant high potential;
- and
- a fourth wiring electrically connected to the logic circuit, the fourth wiring being adapted to be supplied with a second constant high potential,
- wherein the first constant low potential is lower than the second constant low potential, and
- wherein the driver transistor comprises silicon as a semiconductor.
9 more elements
A display device comprising:
- a pixel portion comprising a pixel transistor and a conductive line;
- and
- a driver circuit connected to the conductive line and comprising a logic circuit, the logic circuit comprising:
- an input portion, an output portion, a first transistor, a second transistor, a third transistor and a fourth transistor;
- one of a source and a drain of the first transistor electrically connected to a first wiring, the first wiring being adapted to be supplied with a constant high potential;
- a gate of the first transistor electrically connected to the input portion;
- one of a source and a drain of the second transistor electrically connected to the other of the source and the drain of the first transistor;
- the other of the source and the drain of the second transistor electrically connected to a second wiring, the second wiring being adapted to be supplied with a first constant low potential;
- a gate of the second transistor electrically connected to a third wiring, the third wiring being adapted to be supplied with a first constant potential;
- one of a source and a drain of the third transistor electrically connected to a fourth wiring, the fourth wiring being adapted to be supplied with the constant high potential;
- a gate of the third transistor electrically connected to a fifth wiring, the fifth wiring being adapted to be supplied with a second constant potential;
- one of a source and a drain of the fourth transistor electrically connected to the other of the source and the drain of the third transistor;
- the other of the source and the drain of the fourth transistor electrically connected to a sixth wiring, the sixth wiring being adapted to be supplied with a second constant low potential;
- and
- a gate of the fourth transistor electrically connected to a first electric node at a connection between the first transistor and the second transistor,
- wherein the output portion is electrically connected to a second electric node at a connection between the third transistor and the fourth transistor, and
- wherein the first constant low potential is lower than the second constant low potential.
14 more elements
Dependencies are inferred from the claim text.