# US 8,786,308 B1 · Method and apparatus for providing signal routing control > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,308 B1 - Document ID: US8786308B1 - Status: Granted - Kind: B1 - Application number: 13/656,479 - Filed: 2012-10-19 - Granted: 2014-07-22 - Earliest claimed: 2012-10-19 - Assignees: Altera Corporation - Applicants: Altera Corporation - Inventors: Siang Poh Loh; Chooi Pei Lim; Yee Liang Tan; Kar Keng Chua - Web page: https://patentgrep.com/patent/US8786308B1 ## CPC - H03K 19/17764: for reliability - H03K 19/177: arranged in matrix form - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Integrated circuit packages with a signal routing control through a given direction are disclosed. A disclosed integrated circuit package includes a plurality of interconnects. A first logic circuitry of a first integrated circuit may produce a first signal that may be transmitted to a second integrated circuit. The integrated circuit package further includes interconnect circuitry disposed between the first and second integrated circuits. Multiplexing circuitry may select the first signal from second logic circuitry when the first logic circuitry is defective and may direct the signal as output signal to the second integrated circuit through a given interconnect. ## Claims ### Claim 1 An integrated circuit comprising: an interconnect; a first logic circuitry operable to produce a first signal; a second logic circuitry operable to produce a second signal, wherein the second logic circuitry is activated when the first logic circuitry is defective; and multiplexing circuit operable to receive the first and second signals and to produce an output signal selected from the first and second signals to the interconnect. ### Claim 2 (depends on 1) The integrated circuit defined in claim 1 wherein the first logic circuitry comprises a first programmable logic circuitry and wherein the second logic circuitry comprises a second programmable logic circuitry. ### Claim 3 (depends on 1) The integrated circuit defined in claim 1 further comprising: control circuitry operable to control the multiplexing circuitry to select an output signal from the first and second signals using a control signal. ### Claim 4 (depends on 3) The integrated circuit defined in claim 3 wherein the control circuitry is operable to store information that identifies whether the first programmable logic circuitry is defective and wherein the control circuitry is operable to direct the multiplexing circuitry to select the output signal from the first and second signals based on the stored information. ### Claim 5 (depends on 3) The integrated circuit defined in claim 3 wherein the control signal comprises a static control signal and wherein the control circuitry comprises a programmable memory element that provides the static control signal. ### Claim 6 (depends on 5) The integrated circuit defined in claim 5 further comprising: third and fourth logic circuitries, wherein the third logic circuitry comprises a third programmable logic circuitry and the fourth logic circuitry comprises a fourth programmable logic circuitry; and an additional multiplexing circuit operable to receive an input signal from an external integrated circuit and to transmit the input signal to third and fourth logic circuitries. ### Claim 7 (depends on 6) The integrated circuit defined in claim 6 further comprising: control circuitry that controls additional multiplexing circuit based on information stored at the control circuitry that identifies whether the third programmable logic circuitry is defective. ### Claim 8 (depends on 1) The integrated circuit defined in claim 1 wherein the interconnect is coupled to a corresponding contact pad of an external integrated circuit. ### Claim 9 (depends on 8) The integrated circuit defined in claim 8 wherein the external integrated circuit comprises an interposer. ### Claim 10 (depends on 2) The integrated circuit defined in claim 2 further comprising: a first driver circuit operable to route the first signal from the first logic circuitry to the second logic circuitry. ### Claim 11 A multi-chip package comprising: a first integrated circuit having a first logic circuitry operable to produce a first signal, a second logic circuitry operable to produce a second signal, wherein the second logic circuitry is activated when the first logic circuitry is defective, and a multiplexing circuit operable to produce an output signal selected from the first and second signals; a second integrated circuit; and a plurality of interconnects coupled between the first and second integrated circuits, wherein the output signal is transmitted through a first interconnect of the plurality of interconnects to the second integrated circuit. ### Claim 12 (depends on 11) The multi-chip package defined in claim 11 wherein the second integrated circuit is disposed over the first integrated circuit, wherein the plurality of interconnects includes a plurality of contact pads on the first integrated circuit, and wherein the first interconnect includes a given bump of the plurality of bumps and a given contact pad of the plurality of contact pads. ### Claim 13 (depends on 11) The multi-chip package defined in claim 11 wherein the first integrated circuit comprises a programmable integrated circuit. ### Claim 14 (depends on 11) The multi-chip package defined in claim 11 further comprising: an interposer wherein the second integrated circuit is placed adjacent to the first integrated circuit on the interposer. ### Claim 15 (depends on 11) The multi-chip defined in claim 11, wherein further comprising: a control circuit coupled to the plurality of interconnects, wherein the control circuit is operable to generate the control signal and to provide the control signal to the multiplexing circuit. ### Claim 16 (depends on 12) The multi-chip package defined in claim 12, wherein the plurality of interconnects includes an interposer disposed below the first and the second integrated circuits and a plurality of bumps on the interposer. ### Claim 17 A method of operating an integrated circuit that is coupled to an external integrated circuit by a plurality of interconnects, the method comprising: with a multiplexing circuit, receiving a signal from the external integrated circuit through a given interconnect of the plurality of interconnects; and with the multiplexing circuit, routing the signal to logic circuitry selected from first and second logic circuitry on the integrated circuit. ### Claim 18 (depends on 17) The method defined in claim 17 wherein the integrated circuit comprises a programmable integrated circuit, wherein the first logic circuitry comprises a first programmable logic circuitry, wherein the second logic circuitry comprises routing the signal to a programmable logic circuitry selected from the first and second programmable logic circuitries. ### Claim 19 (depends on 18) The method defined in claim 18 further comprising: with control circuitry, identifying whether the first logic circuitry is defective; and with the control circuitry, providing a control signal to the multiplexing circuit that directs the multiplexing circuit to route the signal from the external integrated circuit to the second logic circuitry in response to identifying that the first logic circuitry is defective. ### Claim 20 (depends on 19) The method defined in claim 19, wherein identifying whether the first logic circuitry is defective comprises: receiving information from a user that identifies whether the first logic circuitry is defective.