# US 8,786,307 B2 · Bias temperature instability-resistant circuits

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- Number: US 8,786,307 B2
- Document ID: US8786307B2
- Status: Granted
- Kind: B2
- Application number: 13/493,371
- Filed: 2012-06-11
- Published: 2013-01-03
- Granted: 2014-07-22
- Earliest claimed: 2011-06-28
- Assignees: Texas Instruments Incorporated
- Applicants: Palkesh Jain
- Inventors: Palkesh Jain
- Web page: https://patentgrep.com/patent/US8786307B2

## CPC

- H03K 19/00315: {in field-effect transistor circuits}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

Standard cells that include transistors subject to aging as a result of BTI-related operating conditions are identified and replaced with BTI-resistant standard cells, for example. The BTI-resistant standard cells are typically functionally equivalent circuits (such as circuits included in standard cells in a design library) and are arranged to ensure that critical transistors are protected (e.g., by either extending recovery times and/or turning the transistor off in response to a critical edge transition).

## Claims

### Claim 1

A Bias Temperature Instability—(BTI-) resistant circuit, comprising a first group of one or more first type transistors that is arranged to cause a first direction transition wherein the state of an output signal of the BTI-resistant circuit is switched from a first state to a second state;
a second group of one or more second type transistors that is arranged to cause a second direction transition wherein the state of an output signal of the BTI-resistant circuit is switched from the second state to the first state, wherein the second type is complementary to the first type; and
a selector that is arranged to cause a first transistor of the first group of one or more first type transistors to transition in a first direction in between each first direction transition caused by a second transistor of the first group of one or more first type transistors, such that active states of the first transistor and the second transistor of the first group are alternated after one or more second direction transitions, which reduces duty cycle of a critical state of the first group of transistors; and wherein the selector is arranged to cause a first transistor of the second group of one or more second type transistors to transition in a second direction in between each second direction transition caused by a second transistor of the second group of one or more second type transistors.

### Claim 2 (depends on 1)

The device of claim 1, wherein the one or more first type transistors are PMOS transistors.

### Claim 3 (depends on 1)

The device of claim 1, wherein the selector is arranged to cause a third transistor of the first group of one or more first type transistors to transition in the first direction between each first direction transition caused by the second transistor of the first group of one or more first type transistors.

### Claim 4 (depends on 1)

The device of claim 1, comprising a latch that is arranged to maintain a state by which the selector determines which transistor of the first group of one or more first type transistors to select to cause a next first direction transition.

### Claim 5 (depends on 1)

The device of claim 1, wherein the selector includes a feedback signal that is provided as an output of the selector and used as an input for the selector, by which the selector determines which transistor of the first group of one or more first type transistors to select to cause the next first direction transition.

### Claim 6 (depends on 1)

The device of claim 1, wherein the device is an inverter.

### Claim 7 (depends on 1)

The device of claim 1, wherein the device is arranged as a BTI-resistant standard cell.

### Claim 8

A Bias Temperature Instability—(BTI-) resistant circuit, comprising:
a first transistor of a first type that is arranged to cause a first direction transition wherein the state of an output signal of the BTI-resistant circuit is switched from a first state to a second state;
a second transistor of a second type that is arranged to cause a second direction transition wherein the state of an output signal of the BTI-resistant circuit is switched from the second state to the first state, wherein the second type is complementary to the first type;
a selector that is arranged to detect the first direction transition and in response to the detection of the first direction transition to change the logic state of the gate of the first transistor before an occurrence of a next second direction transition; and that is arranged to detect the second direction transition and in response to the detection of the second direction transition to change the logic state of the gate of a third transistor of first type before the occurrence of the next first direction transition such that the next first direction transition is done by the third transistor; and
a hold circuit that is arranged to hold the output signal in the second state until the occurrence of the next second direction transition.

### Claim 9 (depends on 8)

The circuit of claim 8, wherein the hold circuit is a weakly driven latch.

### Claim 10 (depends on 8)

The circuit of claim 8, wherein the hold circuit includes end-to-end coupled inverters having a state that is determined by the first type transistor when the first transistor conducts and that is determined by the second type transistor when the second transistor conducts.

### Claim 11 (depends on 8)

The circuit of claim 8, wherein the hold circuit includes a hold transistor of the first type having a source and a drain that is coupled in parallel with the source and drain of the first transistor.

### Claim 12 (depends on 11)

The circuit of claim 11, wherein the selector is arranged to control the gate of the hold transistor in response to the output signal of the BTI-resistant circuit.

### Claim 13 (depends on 8)

The circuit of claim 8, wherein the first type is PMOS.

### Claim 14 (depends on 8)

The circuit of claim 8, a hold circuit that is arranged to hold the output signal in the first state until an occurrence of the next first direction transition.

### Claim 15 (depends on 12)

The circuit of claim 12, wherein the selector is arranged to detect the second direction transition and in response to the detection of the second direction transition to change the logic state of the gate of the second transistor before the occurrence of the next first direction transition.

### Claim 16 (depends on 8)

The circuit of claim 8, wherein the circuit is arranged as a BTI-resistant standard cell.