# US 8,786,130 B1 · Method of forming an electromechanical power switch for controlling power to integrated circuit devices and related devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,130 B1 - Document ID: US8786130B1 - Status: Granted - Kind: B1 - Application number: 13/975,216 - Filed: 2013-08-23 - Granted: 2014-07-22 - Earliest claimed: 2013-08-23 - Assignees: Inoso, LLC - Applicants: Inoso, LLC - Inventors: Kiyoshi Mori; Ziep Tran; Giang T. Dao; Michael E. Ramon - Web page: https://patentgrep.com/patent/US8786130B1 ## CPC - B81C 1/0023: {Packaging together an electronic processing unit die and a micromechanical structure die (MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261)} - H01H 59/0009: {making use of micromechanics} - B81B 2201/018: Switches not provided for in B81B2201/014 - B81B2201/016 - B81B 2207/012: the micromechanical device and the control or processing electronics being separate parts in the same package - B81B 2207/053: of movable structures - B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01) - H01H: ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES (contact cables H01B7/10; electrolytic self-interrupters H01G9/18; emergency protective circuit arrangements H02H; switching by electronic means without contact-making H03K17/00) - B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00) ## Abstract A method of forming an electromechanical power switch for controlling power to integrated circuit (IC) devices and related devices. At least some of the illustrative embodiments are methods comprising forming at least one IC device on a front surface of a semiconductor substrate. The at least one IC device includes at least one circuit block and at least one power switch circuit. A dielectric layer is deposited on the IC device, and first and second electromechanical power switches are formed on the dielectric layer. The first power switch gates a voltage to the circuit block and the second power switch gates the voltage to the IC device. The first power switch is actuated by the power switch circuit, and the voltage to the circuit block is switched off. Alternatively, the second power switch is actuated by the power switch circuit, and the voltage to the IC device is switched off. ## Claims ### Claim 1 A method comprising: providing a semiconductor substrate; forming at least one integrated circuit device on a front surface of the semiconductor substrate, wherein the at least one integrated circuit device includes at least one circuit block and at least one power switch circuit; depositing a dielectric layer on the at least one integrated circuit device; forming a first electromechanical power switch on the dielectric layer, wherein the first electromechanical power switch gates a voltage supply to the at least one circuit block; forming a second electromechanical power switch on the dielectric layer, wherein the second electromechanical power switch gates the voltage supply to the at least one integrated circuit device; actuating the first electromechanical power switch using the at least one power switch circuit; and responsive to actuating the first electromechanical power switch, switching off the voltage supply to the at least one circuit block. ### Claim 2 (depends on 1) The method of claim 1, further comprising: actuating the second electromechanical power switch using the at least one power switch circuit; and responsive to actuating the second electromechanical power switch, switching off the voltage supply to the at least one integrated circuit device. ### Claim 3 (depends on 1) The method of claim 1, wherein each of the first and second electromechanical power switches comprises a structure including at least one selected from a group comprising: a lateral power switch structure; and a vertical power switch structure. ### Claim 4 (depends on 1) The method of claim 1, wherein the at least one circuit block is formed within a specified area of the front surface of the semiconductor substrate, and wherein the first electromechanical power switch is formed on top of the specified area of the front surface of the semiconductor substrate. ### Claim 5 (depends on 1) The method of claim 1, further comprising: forming a third electromechanical power switch on the dielectric layer, wherein the third electromechanical power switch is electrically coupled to the first electromechanical power switch and gates the voltage supply to the at least one circuit block; actuating the third electromechanical power switch using the at least one power switch circuit; and responsive to actuating the third electromechanical power switch, switching off the at least one circuit block. ### Claim 6 (depends on 1) The method of claim 1, further comprising: encapsulating the first and second electromechanical power switches; depositing a second dielectric layer on the encapsulated first and second electromechanical power switches; forming a third electromechanical power switch on the second dielectric layer, wherein the third electromechanical power switch gates the voltage supply to the at least one integrated circuit device; actuating the third electromechanical power switch using the at least one power switch circuit; and responsive to actuating the third electromechanical power switch, switching off the voltage supply to the at least one integrated circuit device. ### Claim 7 (depends on 6) The method of claim 6, further comprising: forming a fourth electromechanical power switch on the second dielectric layer, wherein the fourth electromechanical power switch is electrically coupled to the first electromechanical power switch and gates the voltage supply to the at least one circuit block; actuating the fourth electromechanical power switch using the at least one power switch circuit; and responsive to actuating the fourth electromechanical power switch, switching off the at least one circuit block. ### Claim 8 (depends on 7) The method of claim 7, wherein the at least one circuit block is formed within a specified area of the front surface of the semiconductor substrate, and wherein the first and fourth electromechanical power switches are formed on top of the specified area of the front surface of the semiconductor substrate. ### Claim 9 (depends on 7) The method of claim 7, further comprising: forming a fifth electromechanical power switch on the second dielectric layer, wherein the fifth electromechanical power switch is electrically coupled to the fourth electromechanical power switch and gates the voltage supply to the at least one circuit block; actuating the fifth electromechanical power switch using the at least one power switch circuit; and responsive to actuating the fifth electromechanical power switch, switching off the at least one circuit block. ### Claim 10 (depends on 9) The method of claim 9, wherein the first, second, third, fourth, and fifth electromechanical power switches each comprise a structure including at least one selected from a group comprising: a lateral power switch structure; and a vertical power switch structure. ### Claim 11 (depends on 9) The method of claim 9, wherein the at least one circuit block is formed within a specified area of the front surface of the semiconductor substrate, and wherein the first, fourth, and fifth electromechanical power switches are formed on top of the specified area of the front surface of the semiconductor substrate. ### Claim 12 A semiconductor device comprising: a semiconductor substrate; at least one integrated circuit device on a front surface of the semiconductor substrate, wherein the at least one integrated circuit device includes at least one circuit block and at least one power switch circuit; a dielectric layer on the at least one integrated circuit device; a first electromechanical power switch on the dielectric layer, wherein the first electromechanical power switch gates a voltage supply to the at least one circuit block; and a second electromechanical power switch on the dielectric layer, wherein the second electromechanical power switch gates a voltage supply to the at least one integrated circuit device; wherein the first electromechanical power switch is actuated using the at least one power switch circuit, and wherein the at least one circuit block is switched off in response to the first electromechanical power switch being actuated. ### Claim 13 (depends on 12) The semiconductor device of claim 12, wherein the second electromechanical power switch is actuated using the at least one power switch circuit, and wherein the at least one integrated circuit device is switched off in response to the second electromechanical power switch being actuated. ### Claim 14 (depends on 12) The semiconductor device of claim 12, wherein the at least one circuit block is formed within a specified area of the front surface of the semiconductor substrate, and wherein the first electromechanical power switch is formed on top of the specified area of the front surface of the semiconductor substrate. ### Claim 15 (depends on 12) The semiconductor device of claim 12, further comprising: a third electromechanical power switch on the dielectric layer, wherein the third electromechanical power switch is electrically coupled to the first electromechanical power switch and gates the voltage supply to the at least one circuit block; wherein the third electromechanical power switch is actuated using the at least one power switch circuit, and wherein the at least one circuit block is switched off in response to the third electromechanical power switch being actuated. ### Claim 16 (depends on 12) The semiconductor device of claim 12, further comprising: the first and second electromechanical power switches on the dielectric layer, wherein the first and second electromechanical power switches are encapsulated; a second dielectric layer on the encapsulated first and second electromechanical power switches; and a third electromechanical power switch on the second dielectric layer, wherein the third electromechanical power switch gates the voltage supply to the at least one integrated circuit device; wherein the third electromechanical power switch is actuated using the at least one power switch circuit, and wherein the at least one integrated circuit device is switched off in response to the third electromechanical power switch being actuated. ### Claim 17 (depends on 16) The semiconductor device of claim 16, further comprising: a fourth electromechanical power switch on the second dielectric layer, wherein the fourth electromechanical power switch is electrically coupled to the first electromechanical power switch and gates the voltage supply to the at least one circuit block; wherein the fourth electromechanical power switch is actuated using the at least one power switch circuit, and wherein the at least one circuit block is switched off in response to the fourth electromechanical power switch being actuated. ### Claim 18 (depends on 17) The semiconductor device of claim 17, further comprising: a fifth electromechanical power switch on the second dielectric layer, wherein the fifth electromechanical power switch is electrically coupled to the fourth electromechanical power switch and gates the voltage supply to the at least one circuit block; wherein the fifth electromechanical power switch is actuated using the at least one power switch circuit, and wherein the at least one circuit block is switched off in response to the fifth electromechanical power switch being actuated. ### Claim 19 A data processing system comprising: a system bus; at least one interface device in communication with the system bus; a power management unit in communication with the system bus; a first electromechanical power switch in communication with the power management unit; a second electromechanical power switch in communication with the power management unit; and at least one circuit block in communication with the first electromechanical power switch; wherein the first electromechanical power switch gates a voltage supply to the at least one circuit block and the second electromechanical power switch gates a voltage supply to the data processing system; and wherein the first electromechanical power switch is actuated by the power management unit, and wherein the at least one circuit block is switched off in response to the first electromechanical power switch being actuated. ### Claim 20 (depends on 19) The data processing system of claim 19, wherein the second electromechanical power switch is actuated using the power management unit, and wherein the data processing system is switched off in response to the second electromechanical power switch being actuated.