# US 8,786,112 B2 · Leadframe, semiconductor device, and method of manufacturing the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,112 B2 - Document ID: US8786112B2 - Status: Granted - Kind: B2 - Application number: 13/933,498 - Filed: 2013-07-02 - Published: 2013-10-31 - Granted: 2014-07-22 - Earliest claimed: 2008-08-01 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Kenji Nishikawa - Web page: https://patentgrep.com/patent/US8786112B2 ## CPC - H10P 74/203: {Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects} - H10W 46/00: Marks applied to devices, e.g. for alignment or identification - H10W 70/40: Leadframes - H10W 70/411: {Chip-supporting parts, e.g. die pads} - H10W 90/811: {Multiple chips on leadframes} - H10W 46/301: {for alignment} - H10W 72/07323: {Active alignment, e.g. using optical alignment using marks or sensors} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/075: {of bond wires} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/732: {between stacked chips} - H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a die pad including a first surface and a second surface opposite to the first surface, a first chip arranged in a first area on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged in a second area on the first surface, the second chip including a third side and a fourth side crossing to the third side, a plurality of first marks formed on the first surface, the first marks including a third mark and a fourth mark, a plurality of second marks formed on the first surface, the second marks including a fifth mark and sixth mark. The semiconductor device also includes a wire and a resin encapsulating the first chip, the second chip, and the wire. ## Claims ### Claim 1 A semiconductor device, comprising: a die pad comprising a first surface and a second surface opposite to the first surface; a first chip arranged in a first area on the first surface, the first chip comprising a first side and a second side crossing to the first side; a second chip arranged in a second area on the first surface, the second chip comprising a third side and a fourth side crossing to the third side; a plurality of first marks formed on the first surface, the first marks comprising a third mark and a fourth mark; a plurality of second marks formed on the first surface, the second marks comprising a fifth mark and sixth mark; a wire, one end of the wire connected to the first chip; a resin encapsulating the first chip, the second chip, and the wire; a lead, one end of the lead connected to a second end of the wire, and a part of the lead encapsulated by the resin, wherein the first area is defined as an area surrounded by a first imaginary line, a second imaginary line, a third imaginary line, and a fourth imaginary line in a plan view, wherein the first imaginary line crosses to the third mark and is parallel to the first side of the first chip, wherein the second imaginary line crosses to the third mark and is parallel to the second side of the first chip, wherein the third imaginary line crosses to the fourth mark and is parallel to the first side of the first chip, wherein the fourth imaginary line crosses to the fourth mark and is parallel to the second side of the first chip, wherein the second area is defined as an area surrounded by a fifth imaginary line, a sixth imaginary line, a seventh imaginary line, and a eighth imaginary line in the plan view, wherein the fifth imaginary line crosses to the fifth mark and is parallel to the third side of the second chip, wherein the sixth imaginary line crosses to the fifth mark and is parallel to the fourth side of the second chip, wherein the seventh imaginary line crosses to the sixth mark and is parallel to the third side of the second chip, and wherein the eighth imaginary line crosses to the sixth mark and is parallel to the fourth side of the second chip. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the first area is larger than the second area in the plan view. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the second surface of the die pad is exposed from the resin. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the first mark comprises one of a recess, a projection, and a hole, and wherein the second mark comprises one of a recess, a projection, and a hole. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, wherein the second semiconductor chip is smaller than the first semiconductor chip in the plan view. ### Claim 6 (depends on 1) The semiconductor device according to claim 1, wherein the first mark is positioned between the first semiconductor chip and edges of the die pad, and wherein the second mark is positioned between the second semiconductor chip and said edges of the die pad. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein one of the plurality of first marks comprises a circle in the plan view. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein one of the plurality of second marks comprises a circle in the plan view. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the die pad comprises an octagon in the plan view. ### Claim 10 (depends on 1) The semiconductor device according to claim 1, wherein the first area does not overlap the second area in the plan view. ### Claim 11 (depends on 1) The semiconductor device according to claim 1, wherein the first chip and the second chip do not overlap each other. ### Claim 12 (depends on 1) The semiconductor device according to claim 1, wherein the first side of the first chip is parallel to the third side of the second chip. ### Claim 13 (depends on 1) The semiconductor device according to claim 1, wherein the second side of the first chip is parallel to the fourth side of the second chip. ### Claim 14 (depends on 1) The semiconductor device according to claim 1, wherein the plurality of second mark are different from the plurality of the first mark in at least one of size and geometry. ### Claim 15 (depends on 1) The semiconductor device according to claim 1, wherein the first area overlaps the second area in the plan view. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein the first chip and the second chip overlap each other.