# US 8,786,111 B2 · Semiconductor packages and methods of formation thereof

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- Number: US 8,786,111 B2
- Document ID: US8786111B2
- Status: Granted
- Kind: B2
- Application number: 13/471,291
- Filed: 2012-05-14
- Published: 2013-11-14
- Granted: 2014-07-22
- Earliest claimed: 2012-05-14
- Assignees: Infineon Technologies AG
- Applicants: Edward Fuergut; Joachim Mahler; Khalil Hosseini; Hans-Joerg Timme
- Inventors: Edward Fuergut; Joachim Mahler; Khalil Hosseini; Hans-Joerg Timme
- Web page: https://patentgrep.com/patent/US8786111B2

## CPC

- H10W 74/111: {the semiconductor body being completely enclosed}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10W 20/484: {Interconnections having extended contours, e.g. pads having mesh shape or interconnections comprising connected parallel stripes}
- H10W 70/421: {Shapes or dispositions}
- H10W 70/442: {of multiple leadframes in a single chip}
- H10W 90/00: Package configurations
- H10W 70/461: {specially adapted for cooling}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/0198: {batch processes}
- H10W 72/30: Die-attach connectors
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/342: {relative to the surface, e.g. recessed, protruding}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/534: {being rectangular}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9413: {on encapsulations}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

In one embodiment, a semiconductor package includes a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip. The first major surface includes a first contact region and the second major surface includes a second contact region. The vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction. A back side conductor is disposed at the second contact region of the second major surface. The semiconductor package further includes a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed.

## Claims

### Claim 1

A semiconductor package comprising:
a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip, wherein the first major surface includes a first contact region and the second major surface includes a second contact region, and wherein the vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction;
a front side conductor disposed over the first contact region;
a back side conductor disposed at the second contact region of the second major surface and covering the second major surface; and
a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed, the first encapsulant disposed along a sidewall of the semiconductor chip in a direction of current flow, wherein the first encapsulant covers a first portion of sidewalls of the back side conductor; and
a second encapsulant covering outer sidewalls of the first encapsulant, the front side conductor, and remaining portions of the sidewalls of the back side conductor.

### Claim 2 (depends on 1)

The semiconductor package according to claim 1, wherein the first encapsulant, the vertical semiconductor chip, and the back side conductor are disposed in the second encapsulant.

### Claim 3 (depends on 2)

The semiconductor package according to claim 2, further comprising:
a plurality of contact pads disposed in a major surface of the second encapsulant.

### Claim 4 (depends on 3)

The semiconductor package according to claim 3, wherein the plurality of contact pads comprise a first contact pad coupled to the first contact region through an interconnect disposed in the second encapsulant.

### Claim 5 (depends on 4)

The semiconductor package according to claim 4, wherein the interconnect is one or more of a wire bond, a clamp, clip, strip, ribbon, and a galvanic interconnect.

### Claim 6 (depends on 4)

The semiconductor package according to claim 4, wherein the interconnect is disposed on a sidewall of the first encapsulant.

### Claim 7 (depends on 6)

The semiconductor package according to claim 6, wherein the interconnect is disposed between the first encapsulant and the second encapsulant.

### Claim 8 (depends on 2)

The semiconductor package according to claim 2, wherein the first encapsulant and the second encapsulant are the same material.

### Claim 9 (depends on 2)

The semiconductor package according to claim 2, wherein the first encapsulant and the second encapsulant are different materials.

### Claim 10 (depends on 1)

The semiconductor package according to claim 1, wherein the back side conductor is attached to the vertical semiconductor chip by an adhesive paste, film, or tape.

### Claim 11 (depends on 1)

The semiconductor package according to claim 1, wherein a thickness of the vertical semiconductor chip along the current flow direction is less than about 50 μm.

### Claim 12 (depends on 1)

The semiconductor package according to claim 1, wherein a thickness of the vertical semiconductor chip along the current flow direction is about 5 μm to about 25 μm.

### Claim 13 (depends on 1)

The semiconductor package according to claim 1, wherein the vertical semiconductor chip comprises:
a first transistor having the first contact region and the second contact region, and
a second transistor having a third contact region on the first major surface and a fourth contact region on the second major surface, wherein the second transistor is configured to regulate flow of current from the third contact region to the fourth contact region, and wherein the first transistor is separated from the second transistor by an isolation region.

### Claim 14 (depends on 1)

The semiconductor package according to claim 1, wherein the vertical semiconductor chip comprises a silicon substrate.

### Claim 15 (depends on 1)

The semiconductor package according to claim 1, wherein the vertical semiconductor chip comprises gallium nitride.

### Claim 16 (depends on 1)

The semiconductor package according to claim 1, wherein the vertical semiconductor chip comprises silicon carbide.

### Claim 17

A semiconductor package comprising:
a vertical semiconductor chip having a first major surface on one side of the vertical semiconductor chip and a second major surface on an opposite side of the vertical semiconductor chip, wherein the first major surface includes a first contact region and the second major surface includes a second contact region, and wherein the vertical semiconductor chip is configured to regulate flow of current from the first contact region to the second contact region along a current flow direction;
a back side conductor disposed on a drain contact region of the second major surface;
a first encapsulant in which the vertical semiconductor chip and the back side conductor are disposed, wherein the first encapsulant covers a first portion of sidewalls of the back side conductor;
a second encapsulant surrounding an outer sidewall of the first encapsulant in which the first encapsulant, the vertical semiconductor chip, and the back side conductor are disposed, wherein the second encapsulant covers a remaining portion of the sidewalls of the back side conductor;
a plurality of contact pads disposed on a major surface of the second encapsulant; and
an interconnect disposed in the second encapsulant, the interconnect coupling the first contact region with a pad of the plurality of contact pads.

### Claim 18 (depends on 17)

The semiconductor package according to claim 17, wherein the vertical semiconductor chip comprises:
a first transistor having the first contact region and the second contact region, and
a second transistor having a third contact region on the first major surface and a fourth contact region on the second major surface, wherein the second transistor is configured to regulate flow of current from the third contact region to the fourth contact region, and wherein the first transistor is separated from the second transistor by an isolation region.

### Claim 19 (depends on 17)

The semiconductor package according to claim 17, wherein the vertical semiconductor chip has a slanted sidewall.

### Claim 20 (depends on 17)

The semiconductor package according to claim 17, wherein the vertical semiconductor chip is thinner than the first encapsulant along the current flow direction.

### Claim 21 (depends on 17)

The semiconductor package according to claim 17, wherein a thickness of the vertical semiconductor chip along the current flow direction is less than about 50 μm.

### Claim 22 (depends on 17)

The semiconductor package according to claim 17, wherein a thickness of the vertical semiconductor chip along the current flow direction is about 1 μm to about 100 μm.

### Claim 23 (depends on 17)

The semiconductor package according to claim 17, wherein the interconnect is disposed on a sidewall of the first encapsulant.

### Claim 24 (depends on 23)

The semiconductor package according to claim 23, wherein the interconnection is disposed between the first encapsulant and the second encapsulant.

### Claim 25 (depends on 1)

The semiconductor package according to claim 1, further comprising:
a second vertical semiconductor chip disposed in the first encapsulant, the second vertical semiconductor chip coupled to the vertical semiconductor chip; and
a logic chip disposed in the first encapsulant.

### Claim 26 (depends on 10)

The semiconductor package according to claim 10, wherein the adhesive paste is deposited over a slanted sidewall of the vertical semiconductor chip.

### Claim 27 (depends on 1)

The semiconductor package according to claim 1, further comprising:
a second vertical semiconductor chip disposed in the first encapsulant, wherein the second vertical semiconductor chip has a first major surface on one side of the second vertical semiconductor chip and a second major surface on an opposite side of the second vertical semiconductor chip.

### Claim 28 (depends on 17)

The semiconductor package according to claim 17, further comprising:
a second vertical semiconductor chip disposed in the first encapsulant, wherein the second vertical semiconductor chip has a first major surface on one side of the second vertical semiconductor chip and a second major surface on opposite side of the second vertical semiconductor chip.

### Claim 29 (depends on 28)

The semiconductor package according to claim 28, further comprising a logic chip disposed in the first encapsulant.

### Claim 30 (depends on 1)

The semiconductor package according to claim 1, further comprising a die paddle and an adhesive layer disposed between the back side conductor and the die paddle.