# US 8,786,110 B2 · Semiconductor device and manufacturing method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,110 B2 - Document ID: US8786110B2 - Status: Granted - Kind: B2 - Application number: 13/075,921 - Filed: 2011-03-30 - Published: 2012-03-29 - Granted: 2014-07-22 - Earliest claimed: 2010-09-24 - Assignees: J-Devices Corporation - Applicants: Hisakazu Marutani; Yasunari Iwami; Tomoshige Chikai; Tomoko Takahashi; Osamu Yamagata; Shingo Mitsugi; Chunghao Chen - Inventors: Hisakazu Marutani; Yasunari Iwami; Tomoshige Chikai; Tomoko Takahashi; Osamu Yamagata; Shingo Mitsugi; Chunghao Chen - Web page: https://patentgrep.com/patent/US8786110B2 ## CPC - H10W 74/117: {the substrate having spherical bumps for external connection} - H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)} - H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/614: {the multiple chips being integrally enclosed} - H10W 72/0198: {batch processes} - H10W 74/014: {using batch processing} - H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70) - H10W 90/00: Package configurations - H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers} - H10W 72/07131: {Means for applying material, e.g. for deposition or forming coatings} - H10W 72/073: {of die-attach connectors} - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W 72/241: {Dispositions, e.g. layouts} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/59: Bond pads specially adapted therefor - H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip} - H10W 72/874: {On different surfaces} - H10W 72/9413: {on encapsulations} - H10W 90/20: Configurations of stacked chips - H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL - H10W 90/732: {between stacked chips} - H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device comprising a support plate, a semiconductor element mounted on the support plate and including a circuit element surface having a plurality of first electrodes, a first insulation layer covering the circuit element surface of the semiconductor element, and including a plurality of first apertures exposing the plurality of first electrodes, a second insulation layer covering an upper part of the support plate and side parts of the semiconductor element, and wirings formed on an upper part of the first insulation layer and on an upper part of the second insulation layer, and electrically connected to the corresponding first electrodes. ## Claims ### Claim 1 A semiconductor device comprising: a support plate; a semiconductor element mounted on the support plate and including a circuit element surface having a plurality of first electrodes; a first insulation layer covering at least a portion of an upper part of the circuit element surface of the semiconductor element but not covering side parts of the semiconductor element, and including a plurality of first apertures exposing the plurality of first electrodes; a second insulation layer covering at least a portion of an upper part of the support plate, side parts of the semiconductor element and side parts of the first insulation layer, the first insulation layer not being formed on an upper part of the second insulation layer; and wirings formed on an upper part of the first insulation layer and on an upper part of the second insulation layer, and electrically connected to the corresponding first electrodes. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, further comprising: a third insulation layer formed on the wirings and including a plurality of second apertures partially exposing the wirings wherein a plurality of second electrodes are formed. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein a height of the second insulation layer is the same or less than a height of the first insulation layer. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein a height of the second insulation layer is the same or less than a height of the first insulation layer. ### Claim 5 A stacked type semiconductor device comprising: a support plate; a first semiconductor element mounted on the support plate and including a circuit element surface having a plurality of first electrodes; a first insulation layer covering the circuit element surface of the first semiconductor element, and including a plurality of first apertures exposing the plurality of first electrodes; a second insulation layer covering an upper part of the support plate and side parts of the first semiconductor element and side parts of the first insulation layer; wirings formed on an upper part of the first insulation layer and on an upper part of the second insulation layer, and electrically connected to the corresponding first electrodes; a third insulation layer formed above the semiconductor device and including a plurality of second apertures partially exposing the wirings; a second semiconductor element stacked on the semiconductor device with the third insulation layer interposed between the second semiconductor element and the semiconductor device; a fourth insulation layer covering the circuit element surface of the second semiconductor element, and including a plurality of third apertures exposing a plurality of second electrodes; a fifth insulation layer covering an upper part of the third insulation layer and side parts of the second semiconductor element, and including a plurality of fourth apertures above the second apertures; a plurality of conduction layers formed within the plurality of second apertures of the third insulation layer and being electrically connected to the wirings of the semiconductor device and to a wiring of the second semiconductor element; and a metal layer formed between the semiconductor device and the third insulation layer, and partially covering an upper surface of the semiconductor device. ### Claim 6 (depends on 5) The stacked type semiconductor device according to claim 5, wherein a height of the second insulation layer is the same or less than a height of the first insulation layer. ### Claim 7 A stacked type semiconductor device comprising: a support plate; a first semiconductor element mounted on the support plate and including a circuit element surface having a plurality of first electrodes; a first insulation layer covering the circuit element surface of the first semiconductor element, and including a plurality of first apertures exposing the plurality of first electrodes; a second insulation layer covering an upper part of the support plate and side parts of the first semiconductor element and side parts of the first insulation layer; wirings formed on an upper part of the first insulation layer and on an upper part of the second insulation layer, and electrically connected to the corresponding first electrodes; a third insulation layer formed above the semiconductor device and including a plurality of second apertures partially exposing the wirings; a metal layer formed partially on the third insulation layer, except for the second apertures; a fourth insulation layer formed above the metal layer and including a plurality of third apertures partially exposing the metal layer, and also above the second apertures; a second semiconductor element stacked on the semiconductor device with the fourth insulation layer interposed between the semiconductor device and the second semiconductor element; a fifth insulation layer covering the circuit element surface of the second semiconductor element, and including a plurality of fourth apertures exposing a plurality of second electrodes; a sixth insulation layer covering an upper part of the third insulation layer and side parts of the second semiconductor element, and including a plurality of fifth apertures above the second and third apertures; a plurality of conduction poles formed within the plurality of second, fifth and third apertures of the third, sixth and fourth insulation layers, respectively, and being electrically connected to the wirings of the semiconductor device and the metal layer; and second wirings formed on an upper part of the fifth insulation layer and on an upper part of the sixth insulation layer and electrically connected to the second electrodes and the plurality of conduction poles, and some wirings connect between the second electrodes and the plurality of conduction poles. ### Claim 8 (depends on 7) The stacked type semiconductor device according to claim 7, wherein a height of the second insulation layer is the same or less than a height of the first insulation layer.