# US 8,786,106 B2 · Semiconductor device and method for manufacturing semiconductor device

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- Number: US 8,786,106 B2
- Document ID: US8786106B2
- Status: Granted
- Kind: B2
- Application number: 14/059,489
- Filed: 2013-10-22
- Published: 2014-03-20
- Granted: 2014-07-22
- Earliest claimed: 2004-11-16
- Assignees: Rohm Co., Ltd.
- Applicants: Rohm Co., Ltd.
- Inventors: Osamu Miyata; Masaki Kasai; Shingo Higuchi
- Web page: https://patentgrep.com/patent/US8786106B2

## CPC

- H10W 74/134: {the encapsulations being in grooves in the semiconductor body}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/43: Layouts of interconnections
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 72/0198: {batch processes}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 74/127: {characterised by arrangements for sealing or adhesion}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 46/503: {Located in scribe lines}
- H10W 70/652: Cross-sectional shapes
- H10W 70/656: Fan-in layouts
- H10W 70/66: Conductive materials thereof
- H10W 70/69: Insulating materials thereof
- H10W 72/019: {of bond pads}
- H10W 72/07251: {characterised by changes in properties of the bump connectors during connecting}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/251: {Materials}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/40: characterised by their materials
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An inventive semiconductor device includes a semiconductor chip having a passivation film, and a sealing resin layer provided over the passivation film for sealing a front side of the semiconductor chip. The sealing resin layer extends to a side surface of the passivation film to cover the side surface.

## Claims

### Claim 1

A semiconductor device comprising;
a semiconductor chip having a passivation film on part of a front surface thereof which is a functional surface;
a stress relieving layer having an upper surface and a side surface provided on the passivation film;
a sealing resin layer provided on the stress relieving layer for sealing the front surface of the semiconductor chip, the sealing resin layer extending to a side surface of the stress relieving layer; and
a rewiring provided on the upper surface of the stress relieving layer, the rewiring having a side surface positioned inside of the stress relieving layer such that the upper surface of the stress relieving layer is partly exposed;
wherein the sealing resin layer is in direct contact with the semiconductor chip without the passivation film and in contact with the upper surface of the stress relieving layer, and
the sealing resin layer entirely covers the stress relieving layer, the passivation film and the rewiring.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, further comprising a metal ball disposed on the sealing resin layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor chip includes a semiconductor substrate of silicon.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the semiconductor chip has a rectangular shape as seen in plan.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the passivation film contains at least one of silicon oxide and silicon nitride.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein the passivation film has a pad opening to expose an electrode pad.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the pad opening exposes a part of an internal interconnection of a metal provided in the front surface of the semiconductor chip as the electrode pad.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the metal includes aluminum.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1, wherein the stress relieving layer includes polyimide.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1, wherein the rewiring is electrically connected to an electrode pad through a through-hole formed in the stress relieving layer at a position opposed to the electrode pad, and the electrode pad is exposed through a pad opening formed in the passivation film.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the sealing resin layer includes an epoxy resin.