# US 8,786,104 B2 · Three-dimensional multichip module > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,786,104 B2 - Document ID: US8786104B2 - Status: Granted - Kind: B2 - Application number: 14/068,748 - Filed: 2013-10-31 - Published: 2014-02-27 - Granted: 2014-07-22 - Earliest claimed: 2005-11-29 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Hans-Joachim Barth - Web page: https://patentgrep.com/patent/US8786104B2 ## CPC - H10W 90/00: Package configurations - H10W 40/00: Arrangements for thermal protection or thermal control (integrated devices comprising arrangements for thermal protection H10D89/60) - H10W 90/288: {characterised by arrangements for thermal management of the stacked chips} - H10W 90/722: {between stacked chips} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A three-dimensional multichip module includes a first integrated circuit chip having at least one first high-temperature functional area and one first low-temperature functional area, and at least one second integrated circuit chip having a second high-temperature functional area and a second low-temperature functional area. The second high-temperature functional area is arranged opposite the first low-temperature functional area. As an alternative, at least one low-temperature chip having only one low-temperature functional area can also be arranged between the first and second chips. ## Claims ### Claim 1 A three-dimensional multichip module comprising: a first integrated circuit chip having a first high-temperature functional area with high emission of heat and a first low-temperature functional area with low emission of heat; a second integrated circuit chip having a second high-temperature functional area with high emission of heat and a second low-temperature functional area with low emission of heat, the first and second integrated circuit chips being electrically connected to one another and being arranged opposite one another with regard to their main surfaces; and a third integrated circuit chip having a third low-temperature functional area with low emission of heat and no high temperature area with high emission of heat, the third integrated circuit chip disposed between the first integrated circuit chip and the second integrated circuit chip, wherein the second high-temperature functional area of the second integrated circuit chip is arranged on a side of the first low-temperature functional area of the first integrated circuit chip, and wherein the first high-temperature functional area of the first integrated circuit chip is arranged on a side of the second low-temperature functional area of the second integrated circuit chip. ### Claim 2 (depends on 1) The three-dimensional multichip module as claimed in claim 1, wherein the first integrated circuit chip is identical to the second integrated circuit chip. ### Claim 3 (depends on 1) The three-dimensional multichip module as claimed in claim 1, wherein a first high-temperature functional element in the first high-temperature functional area of the first integrated circuit chip is electrically connected to a second low-temperature functional element in the second low-temperature functional area of the second integrated circuit chip. ### Claim 4 (depends on 3) The three-dimensional multichip module as claimed in claim 3, wherein the electrical connection is realized only if a first total wiring length between the first high-temperature functional element and a suitable second low-temperature functional element of the second integrated circuit is shorter than a second total wiring length between the first high-temperature functional element and a suitable first low-temperature functional element of the first integrated circuit. ### Claim 5 (depends on 1) The three-dimensional multichip module as claimed in claim 1, wherein the first and second integrated circuit chips comprise microprocessor or microcontroller components. ### Claim 6 (depends on 1) The three-dimensional multichip module as claimed in claim 1, wherein the first to second high-temperature functional areas comprise processor cores or controller cores and the first to third low-temperature functional areas comprise memory units. ### Claim 7 (depends on 6) The three-dimensional multichip module as claimed in claim 6, wherein the memory units comprise cache memories, SRAM, DRAM, EEPROM, flash memories, other nonvolatile memories, registers and/or bus control units. ### Claim 8 (depends on 1) The three-dimensional multichip module as claimed in claim 1, wherein the first and second high-temperature functional areas comprise power semiconductor components having regions with high emission of heat. ### Claim 9 A three-dimensional multichip module comprising: a first integrated circuit chip having a first high-temperature functional area with high emission of heat and a first low-temperature functional area with low emission of heat, the first integrated circuit chip having a first main surface; a second integrated circuit chip having a second high-temperature functional area with high emission of heat and a second low-temperature functional area with low emission of heat, the second integrated circuit chip having a first main surface; and a third integrated circuit chip having a third low-temperature functional area with low emission of heat and no high temperature area with high emission of heat, the third integrated circuit chip having a first main surface and a second main surface, wherein the first main surface of the first integrated circuit is directly electrically connected to the first main surface of the third integrated circuit through a first metal or metal alloy bond, wherein the first main surface of the second integrated circuit is directly electrically connected to the second main surface of the third integrated circuit through a second metal or metal alloy bond, and wherein the first to third integrated circuit chips form a first sidewall and a second sidewall of the three-dimensional multichip module. ### Claim 10 (depends on 9) The three-dimensional multichip module as claimed in claim 9, further comprising the first high-temperature functional area of the first integrated circuit is arranged on the first sidewall of the three-dimensional multichip module, and wherein the second high-temperature functional area of the second integrated circuit is arranged on the second sidewall of the three-dimensional multichip module. ### Claim 11 (depends on 9) The three-dimensional multichip module as claimed in claim 9, wherein the first sidewall and the second sidewall are opposite to each another. ### Claim 12 (depends on 9) The three-dimensional multichip module as claimed in claim 9, wherein the first sidewall and the second sidewall are next to each other. ### Claim 13 (depends on 9) The three-dimensional multichip module as claimed in claim 9, wherein the third low-temperature functional area comprises memory units. ### Claim 14 (depends on 9) The three-dimensional multichip module as claimed in claim 9, wherein the third low-temperature functional area comprises a L2 cache memory. ### Claim 15 (depends on 9) The three-dimensional multichip module as claimed in claim 9, wherein the first main surface of the first integrated circuit chip and the first main surface of the third integrated circuit chip are electrically connected by a face-to-face bond. ### Claim 16 (depends on 15) The three-dimensional multichip module as claimed in claim 15, wherein the first main surface of the second integrated circuit chip and the second main surface of the third integrated circuit chip are electrically connected by a through via bond. ### Claim 17 (depends on 9) The three-dimensional multichip module as claimed in claim 9, wherein the first main surface of the first integrated circuit chip and the first main surface of the third integrated circuit chip are electrically connected by a through via bond. ### Claim 18 (depends on 17) The three-dimensional multichip module as claimed in claim 17, wherein the first main surface of the second integrated circuit chip and the second main surface of the third integrated circuit chip are electrically connected by a face-to-face bond. ### Claim 19 A three-dimensional multichip module comprising: a first integrated circuit chip having a first high-temperature functional area with high emission of heat and a first low-temperature functional area with low emission of heat; a second integrated circuit chip having a second high-temperature functional area with high emission of heat and a second low-temperature functional area with low emission of heat; and a third integrated circuit chip having a third low-temperature functional area with low emission of heat and no high temperature area with high emission of heat, the first to third integrated circuit chips being electrically connected to each other, wherein the first and the second integrated circuit chips form a first sidewall, a second sidewall, a third sidewall and a fourth sidewall of the three-dimensional multichip module, wherein the first high-temperature functional area of the first integrated circuit is located at the first sidewall of the three-dimensional multichip module, and wherein the second high-temperature functional area of the second integrated circuit is located at the second sidewall of the three dimensional multichip module. ### Claim 20 (depends on 19) The three-dimensional multichip module as claimed in claim 19, wherein the first and second integrated circuit chips are identical.