# US 8,786,102 B2 · Semiconductor device and method of manufacturing the same

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- Number: US 8,786,102 B2
- Document ID: US8786102B2
- Status: Granted
- Kind: B2
- Application number: 14/051,189
- Filed: 2013-10-10
- Published: 2014-02-06
- Granted: 2014-07-22
- Earliest claimed: 2009-09-10
- Assignees: PS4 Luxco S.a.r.l.
- Applicants: Elpida Memory, Inc.
- Inventors: Masanori Yoshida; Fumitomo Watanabe
- Web page: https://patentgrep.com/patent/US8786102B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 46/301: {for alignment}
- H10W 72/0198: {batch processes}
- H10W 72/07141: {Means for applying energy, e.g. ovens or lasers}
- H10W 72/072: {of bump connectors}
- H10W 72/07223: {Active alignment, e.g. using optical alignment using marks or sensors}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/30: Die-attach connectors
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first wiring board, a second semiconductor chip, and a second seal. The first wiring board includes a first substrate, a first semiconductor chip, and a first seal. The first semiconductor chip is disposed on the first substrate. The first seal is disposed on the first substrate. The first seal surrounds the first semiconductor chip. The first seal has the same thickness as the first semiconductor chip. The second semiconductor chip is stacked over the first semiconductor chip. The first semiconductor chip is between the second semiconductor chip and the first substrate. The second semiconductor chip is greater in size in plan view than the first semiconductor chip. The second seal seals at least a first gap between the first semiconductor chip and the second semiconductor chip.

## Claims

### Claim 1

A device comprising:
a first semiconductor chip including a first surface, a second surface opposite to the first surface, and side surfaces joined to the first and second surfaces to define edges thereof;
a plurality of first electrodes formed on the first surface of the first semiconductor chip;
a plurality of second electrodes formed on the second surface of the first semiconductor chip, the second electrodes being electrically coupled to the first electrodes, respectively:
a first sealing resin surrounding the side surfaces of the first semiconductor chip, the first sealing resin being in direct contact with the side surfaces of the first semiconductor chip and including a lower surface which is substantially coplanar with the second surface of the first semiconductor chip, the lower surface of the first sealing resin including a plurality of portions;
a first insulating layer formed in contact with the second surface of the first semiconductor chip and with the lower surface of the first sealing resin so as to expose the second electrodes from the first insulating layer;
a plurality of land electrodes formed over the first insulating layer apart from the first semiconductor chip, each of the land electrodes being vertically aligned with an associated one of the portions of the lower surface of the first sealing resin;
a plurality of rewiring layers each connected to an associated one of the second electrodes and elongated over the first insulating layer to reach a corresponding one of the land electrodes; and
a second insulating layer formed on the first insulating layer and the rewiring layers so that the land electrodes expose from the second insulating layer,
wherein the first semiconductor chi includes a plurality of through electrodes therein, and the first electrodes are electrically coupled to the second electrodes via the through electrodes, respectively.

### Claim 2 (depends on 1)

The device as claimed in claim 1, further comprising:
a second semiconductor chip stacked over the first surface of the first semiconductor chip, the first electrodes being disposed between the first and second semiconductor chips.

### Claim 3 (depends on 2)

The device as claimed in claim 2, further comprising:
a second sealing resin provided between the first and second semiconductor chips, the first electrodes being covered with the second sealing resin.

### Claim 4 (depends on 2)

The device as claimed in claim 2, wherein the second semiconductor chip is greater in size than the first semiconductor chip.

### Claim 5 (depends on 2)

The device as claimed in claim 2, further comprising:
a third semiconductor chip staked over the second semiconductor chip, the second semiconductor chip being disposed between the first and third semiconductor chips.

### Claim 6 (depends on 2)

The device as claimed in claim 2, wherein the first semiconductor chip is an interface chip or a logic chip, and the second semiconductor chip is a memory chip.

### Claim 7 (depends on 1)

The device as claimed in claim 1, further comprising:
a supporting substrate stacked over the first surface of the first semiconductor chip, the first semiconductor chip being disposed between the first insulating layer and the supporting substrate.

### Claim 8 (depends on 1)

The device as claimed in claim 1, further comprising:
a chip stacked structure including a plurality of second semiconductor chips that are stacked with one another, the chip stacked structure including a plurality of third electrodes on a lowermost one of the second semiconductor chips, the chip stacked structure being staked over the first surface of the first semiconductor chip, and the third electrodes being electrically coupled to the first electrodes.

### Claim 9 (depends on 8)

The device as claimed in claim 8, wherein the plurality of second semiconductor chips include a plurality of through electrodes, and the second semiconductor chips are electrically coupled to one another via the through electrodes.

### Claim 10

A device comprising:
a first semiconductor chip including a first surface, a second surface opposite to the first surface, and side surfaces joined to the first and second surfaces to define edges thereof;
a plurality of first electrodes formed on the first surface of the first semiconductor chip;
a plurality of second electrodes formed on the second surface of the first semiconductor chip, the second electrodes being electrically coupled to the first electrodes, respectively;
a first sealing resin surrounding the side surfaces of the first semiconductor chip, the first sealing resin being in direct contact with the side surfaces of the first semiconductor chip and including a lower surface which is substantially coplanar with the second surface of the first semiconductor chip, the lower surface of the first sealing resin including a plurality of portions;
a first insulating layer formed in contact with the second surface of the first semiconductor chip and with the lower surface of the first sealing resin so as to expose the second electrodes from the first insulating layer;
a plurality of land electrodes formed over the first insulating layer apart from the first semiconductor chip, each of the land electrodes being vertically aligned with an associated one of the portions of the lower surface of the first sealing resin;
a plurality of rewiring layers each connected to an associated one of the second electrodes and elongated over the first insulating layer to reach a corresponding one of the land electrodes;
a second insulating layer formed on the first insulating layer and the rewiring layers so that the land electrodes expose from the second insulating layer; and
a second semiconductor chip stacked over the first surface of the first semiconductor chip, the first electrodes being disposed between the first and second semiconductor chips,
wherein the second semiconductor chip includes a third surface, a fourth surface opposite to the third surface, side surfaces joined to the third and fourth surface to defined edges thereof and a plurality of third electrodes formed on the third surface, the second semiconductor chip being stacked over the first surface of the first semiconductor chip so that the fourth surface faces the first semiconductor chip, and the device further comprising:
a second sealing resin surrounding the side surfaces of the second semiconductor chip, the second sealing resin being in direct contact with the side surfaces of the second semiconductor chip and including an upper surface which is substantially coplanar with the third surface of the second semiconductor chip;
a third insulating layer formed in contact with the third surface of the second semiconductor chip and with the upper surface of the second sealing resin;
a plurality of second land electrodes formed over the third insulating layer apart from the second semiconductor chip; and
a plurality of second rewiring layers each connected to an associated one of the third electrodes and elongated over the third insulating layer to reach a corresponding one of the second land electrodes.

### Claim 11

A device comprising:
a first semiconductor chip including a first surface, a second surface opposite to the first surface, and side surfaces joined to the first and second surfaces to define edges thereof;
a plurality of first electrodes formed on the first surface of the first semiconductor chip;
a plurality of second electrodes formed on the second surface of the first semiconductor chip, the second electrodes being electrically coupled to the first electrodes, respectively;
a first sealing resin surrounding the side surfaces of the first semiconductor chip, the first sealing resin being in direct contact with the side surfaces of the first semiconductor chip and including a lower surface which is substantially coplanar with the second surface of the first semiconductor chip, the lower surface of the first sealing resin including a plurality of portions;
a first insulating layer formed in contact with the second surface of the first semiconductor chip and with the lower surface of the first scaling resin so as to expose the second electrodes from the first insulating layer;
a plurality of land electrodes formed over the first insulating layer apart from the first semiconductor chip, each of the land electrodes being vertically aligned with an associated one of the portions of the lower surface of the first sealing resin;
a plurality of rewiring layers each connected to an associated one of the second electrodes and elongated over the first insulating layer to reach a corresponding one of the land electrodes;
a second insulating layer formed on the first insulating layer and the rewiring layers so that the land electrodes expose from the second insulating layer; and
a second semiconductor chip including a plurality of third electrodes thereon, the second semiconductor chip being stacked over the first surface of the first semiconductor chip, the third electrodes being electrically coupled to the first electrodes,
wherein the first semiconductor chip includes a plurality of through electrodes therein, the first electrodes are electrically coupled to the second electrodes via the through electrodes, respectively.

### Claim 12 (depends on 11)

The device as claimed in claim 11, further comprising:
a second sealing resin provided between the first and second semiconductor chips, the first electrodes being covered with the second sealing resin.

### Claim 13 (depends on 11)

The device as claimed in claim 11, wherein the second semiconductor chip is greater in size than the first semiconductor chip.

### Claim 14 (depends on 11)

The device as claimed in claim 11, further comprising:
a supporting substrate stacked over the second semiconductor chip, the second semiconductor chip being disposed between the first semiconductor chip and the supporting substrate.

### Claim 15 (depends on 11)

The device as claimed in claim 11, further comprising:
a third semiconductor chip staked over the second semiconductor chip, the second semiconductor chip being disposed between the first and third semiconductor chips.

### Claim 16 (depends on 11)

The device as claimed in claim 11, wherein the second semiconductor chip includes a plurality of through electrodes, and the through electrodes are electrically coupled to the third electrodes.

### Claim 17 (depends on 11)

The device as claimed in claim 11, wherein the first semiconductor chip is an interface chip or a logic chip, and the second semiconductor chip is a memory chip.

### Claim 18

A device comprising:
a first semiconductor chip including a first surface, a second surface opposite to the first surface, and side surfaces joined to the first and second surfaces to define edges thereof;
a plurality of first electrodes formed on the first surface of the first semiconductor chip;
a plurality of second electrodes formed on the second surface of the first semiconductor chip, the second electrodes being electrically coupled to the first electrodes, respectively;
a first sealing resin surrounding the side surfaces of the first semiconductor chip, the first sealing resin being in direct contact with the side surfaces of the first semiconductor chip and including a lower surface which is substantially coplanar with the second surface of the first semiconductor chip, the lower surface of the first sealing resin including a plurality of portions;
a first insulating layer formed in contact with the second surface of the first semiconductor chip and with the lower surface of the first sealing resin so as to expose the second electrodes from the first insulating layer;
a plurality of land electrodes formed over the first insulating layer apart from the first semiconductor chip, each of the land electrodes being vertically aligned with an associated one of the portions of the lower surface of the first sealing resin;
a plurality of rewiring layers each connected to an associated one of the second electrodes and elongated over the first insulating layer to reach a corresponding one of the land electrodes;
a second insulating layer formed on the first insulating layer and the rewiring layers so that the land electrodes expose from the second insulating layer; and
a second semiconductor chip including a plurality of third electrodes thereon, the second semiconductor chip being stacked over the first surface of the first semiconductor chip, the third electrodes being electrically coupled to the first electrodes,
wherein the second semiconductor chip includes a third surface, a fourth surface opposite to the third surface and side surfaces joined to the third and fourth surface to defined edges thereof and a plurality of fourth electrodes formed on the third surface, the second semiconductor chip being stacked over the first surface of the first semiconductor chip so that the fourth surface faces the first semiconductor chip, and the device further comprising:
a second sealing resin surrounding the side surfaces of the second semiconductor chip, the second sealing resin being in direct contact with the side surfaces of the second semiconductor chip and including an upper surface which is substantially coplanar with the third surface of the second semiconductor chip;
a third insulating layer formed in contact with the third surface of the second semiconductor chip and with the upper surface of the second sealing resin;
a plurality of second land electrodes formed over the third insulating layer apart from the second semiconductor chip; and
a plurality of second rewiring layers each connected to an associated one of the third electrodes and elongated over the third insulating layer to reach a corresponding one of the second land electrodes.