# US 8,786,100 B2 · Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die

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- Number: US 8,786,100 B2
- Document ID: US8786100B2
- Status: Granted
- Kind: B2
- Application number: 13/664,626
- Filed: 2012-10-31
- Published: 2013-03-07
- Granted: 2014-07-22
- Earliest claimed: 2010-03-15
- Assignees: STATS ChipPAC, Ltd.
- Applicants: STATS ChipPAC, Ltd.
- Inventors: Yaojian Lin; Kang Chen; Jianmin Fang; Xia Feng
- Web page: https://patentgrep.com/patent/US8786100B2

## CPC

- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H10W 20/42: Vias, e.g. via plugs
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/0198: {batch processes}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 46/603: {Formed on wafers or substrates before dicing and remaining on chips after dicing}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor wafer has a plurality of first semiconductor die. A first conductive layer is formed over an active surface of the die. A first insulating layer is formed over the active surface and first conductive layer. A repassivation layer is formed over the first insulating layer and first conductive layer. A via is formed through the repassivation layer to the first conductive layer. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is mounted to a temporary carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is removed. A second insulating layer is formed over the repassivation layer and encapsulant. A second conductive layer is formed over the repassivation layer and first conductive layer. A third insulating layer is formed over the second conductive layer and second insulating layer. An interconnect structure is formed over the second conductive layer.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor wafer including a plurality of semiconductor die;
a first contact pad formed on a surface of the semiconductor die;
an insulating layer formed over the semiconductor die and first contact pad;
a passivation layer formed over the insulating layer and first contact pad; and
a conductive via formed through the passivation layer and extending to the first contact pad.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further including an interconnect structure formed over the passivation layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, further including an opening formed in the insulating layer.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein a width of the opening is greater than a width of the conductive via.

### Claim 5 (depends on 3)

The semiconductor device of claim 3, wherein the passivation layer extends through the opening and to the first contact pad.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, further including a conductive layer disposed between the passivation layer and insulating layer.

### Claim 7

A semiconductor device, comprising:
a semiconductor die;
a first conductive layer formed on the semiconductor die;
a first insulating layer formed over the semiconductor die and first conductive layer;
a second insulating layer formed over the first insulating layer and first conductive layer; and
a via formed through the second insulating layer and extending to the first conductive layer.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, further including an interconnect structure formed over the second insulating layer.

### Claim 9 (depends on 7)

The semiconductor device of claim 7, further including an opening formed in the first insulating layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein a width of the opening is greater than a width of the via.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the second insulating layer extends through the opening and to the first conductive layer.

### Claim 12 (depends on 7)

The semiconductor device of claim 7, further including a second conductive layer disposed between the first insulating layer and second insulating layer.

### Claim 13 (depends on 7)

The semiconductor device of claim 7, further including a second conductive layer formed in the via.

### Claim 14

A semiconductor device, comprising:
a first conductive layer;
a first insulating layer formed over the first conductive layer;
a second insulating layer formed over the first insulating layer; and
a via formed through the second insulating layer exposing the first conductive layer.

### Claim 15 (depends on 14)

The semiconductor device of claim 14, further including an interconnect structure formed over the second insulating layer.

### Claim 16 (depends on 14)

The semiconductor device of claim 14, further including an opening formed in the first insulating layer.

### Claim 17 (depends on 16)

The semiconductor device of claim 16, wherein a width of the opening is greater than a width of the via.

### Claim 18 (depends on 14)

The semiconductor device of claim 14, further including a second conductive layer disposed in the via.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, further including a third conductive layer formed over the second conductive layer.

### Claim 20

A semiconductor device, comprising:
a conductive layer;
a first insulating layer formed over a surface of the conductive layer;
a second insulating layer formed over the first insulating layer and conductive layer; and
a via extending through the second insulating layer to the surface of the conductive layer.

### Claim 21 (depends on 20)

The semiconductor device of claim 20, further including an interconnect structure formed over the second insulating layer.

### Claim 22 (depends on 20)

The semiconductor device of claim 20, further including an opening formed in the first insulating layer.

### Claim 23 (depends on 22)

The semiconductor device of claim 22, wherein a width of the opening is greater than a width of the via.

### Claim 24 (depends on 22)

The semiconductor device of claim 22, wherein the second insulating layer extends through the opening and to the conductive layer.

### Claim 25 (depends on 20)

The semiconductor device of claim 20, further including a substrate disposed over the conductive layer and the first insulating layer.