# US 8,786,098 B2 · Semiconductor element having conductive vias and semiconductor package having a semiconductor element with conductive vias and method for making the same

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,786,098 B2
- Document ID: US8786098B2
- Status: Granted
- Kind: B2
- Application number: 13/092,866
- Filed: 2011-04-22
- Published: 2012-04-12
- Granted: 2014-07-22
- Earliest claimed: 2010-10-11
- Assignees: Advanced Semiconductor Engineering, Inc.
- Applicants: Meng-Jen Wang
- Inventors: Meng-Jen Wang
- Web page: https://patentgrep.com/patent/US8786098B2

## CPC

- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/216: {characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes}
- H10W 70/635: {Through-vias}
- H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/00: Package configurations
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present invention relates to a semiconductor element having conductive vias and a semiconductor package having a semiconductor element with conductive vias and a method for making the same. The semiconductor element having conductive vias includes a silicon substrate and at least one conductive via. The thickness of the silicon substrate is substantially in a range from 75 to 150 μm. The conductive via includes a first insulation layer and a conductive metal, and the thickness of the first insulation layer is substantially in a range from 5 to 19 μm. Using the semiconductor element and the semiconductor package of the present invention, the electrical connection between the conductive via and the other element can be ensured, and the electrical connection between the silicon substrate and the other semiconductor element can be ensured, so as to raise the yield rate of a product. Moreover, by employing the method of the present invention, warpage and shift of the silicon substrate can be avoided during the reflow process, so as to conduct the reflow process only a single time in the method of the present invention, thereby simplifying the subsequent process and reducing cost.

## Claims

### Claim 1

A semiconductor element, comprising:
a silicon substrate, having a plurality of through holes, each of the through holes including a conductive via formed therein, wherein the conductive via includes an insulation layer disposed on a side wall of the through hole, defining a first central hole, the first central hole including a conductive metal disposed therein;
wherein, for at least one of the through holes, a difference between the radius of the through hole and a radius of the first central hole within the through hole is substantially in a range from 5 to 19 μm; and
wherein the conductive metal forms a hollow cylinder structure, the hollow cylinder structure defining a second central hole, and each of the conductive vias further comprises a second insulation layer disposed in the second central hole.

### Claim 2 (depends on 1)

The semiconductor element as claimed in claim 1, wherein a thickness of the silicon substrate is substantially in a range from 75 to 150 μm.

### Claim 3 (depends on 1)

The semiconductor element as claimed in claim 1, wherein a diameter of at least one of the conductive vias is substantially in a range from 25 to 50 μm.

### Claim 4 (depends on 1)

The semiconductor element as claimed in claim 1, wherein a thickness of the conductive metal is greater than or equal to about 6 μm.

### Claim 5 (depends on 1)

The semiconductor element as claimed in claim 1, further comprising a passivation layer, wherein the passivation layer has a plurality of openings and a plurality of metal pads, wherein each of the metal pads is disposed in each of the openings, and electrically connected to the conductive metal.

### Claim 6 (depends on 5)

The semiconductor element as claimed in claim 5, wherein a thickness of each of the metal pads is greater than or equal to about 4.5 μm.

### Claim 7 (depends on 1)

The semiconductor element as claimed in claim 1, wherein a diameter of the conductive metal is substantially in a range from 12 to 40 μm.

### Claim 8

A semiconductor package having a semiconductor element, comprising:
a silicon substrate, having a plurality of through holes, each of the through holes including a conductive via formed therein, wherein the conductive via includes an insulation layer disposed on a side wall of the through hole, defining a first central hole, the first central hole including a conductive metal disposed therein; and
at least one chip, disposed on the semiconductor element, and electrically connected to the conductive vias of the semiconductor element;
wherein, for at least one of the through holes, a difference between the radius of the through hole and a radius of the first central hole within the through hole is substantially in a range from 5 to 19 μm; and
wherein the conductive metal forms a hollow cylinder structure, the hollow cylinder structure defining a second central hole, and each of the conductive vias further comprises a second insulation layer disposed in the second central hole.

### Claim 9 (depends on 8)

The semiconductor package as claimed in claim 8, wherein a thickness of the silicon substrate is substantially in a range from 75 to 150 μm.

### Claim 10 (depends on 8)

The semiconductor package as claimed in claim 8, wherein a diameter of at least one of the conductive vias is substantially in a range from 25 to 50 μm.

### Claim 11 (depends on 8)

The semiconductor package as claimed in claim 8, wherein the semiconductor element further comprises:
a first passivation layer, disposed on a first surface, and having a plurality of first openings;
a second passivation layer, disposed on a second surface, and having a plurality of second openings;
a plurality of first metal pads, wherein each of the first metal pads is disposed in each of the first openings, and electrically connected to the conductive metal; and
a plurality of second metal pads, wherein each of the first metal pads is disposed in each of the second openings, and electrically connected to the conductive metal.

### Claim 12 (depends on 11)

The semiconductor package as claimed in claim 11, wherein the thickness of each of the first metal pads or each of the second metal pads is greater than or equal to about 4.5 μm.

### Claim 13 (depends on 8)

The semiconductor package as claimed in claim 8, further comprising a carrier, wherein the semiconductor element is disposed on the carrier and the carrier is a silicon substrate body or an organic substrate body.

### Claim 14 (depends on 8)

The semiconductor package as claimed in claim 8, wherein a diameter of the conductive metal is substantially in a range from 12 to 40 μm.

### Claim 15

A method for making a semiconductor package having a semiconductor element with conductive vias, comprising:
(a) providing a carrier;
(b) disposing a semiconductor element on the carrier, wherein the semiconductor element comprises a silicon substrate and conductive vias, the silicon substrate has a first surface, a second surface and through holes, the through holes penetrate the silicon substrate, the thickness of the silicon substrate is substantially in a range from 75 to 150 μm, the conductive vias penetrate the silicon substrate and each of the conductive vias comprises a first insulation layer and a conductive metal, the first insulation layer is disposed on a side wall of each of the through holes and defines a first central hole, and the conductive metal is disposed in the first central hole;
wherein, for at least one of the through holes, a difference between the radius of the through hole and a radius of the first central hole within the through hole is substantially in a range from 5 to 19 μm; and
wherein the conductive metal forms a hollow cylinder structure, the hollow cylinder structure defining a second central hole, and each of the conductive vias further comprises a second insulation layer disposed in the second central hole;
(c) disposing a plurality of chips on the semiconductor element; and
(d) conducting a reflow process.

### Claim 16 (depends on 15)

The method as claimed in claim 15, wherein in step (b), the conductive vias and the carrier are electrically connected by a plurality of first bumps.

### Claim 17 (depends on 15)

The method as claimed in claim 15, wherein in step (c), the conductive vias and the chips are electrically connected by a plurality of second bumps.

### Claim 18 (depends on 15)

The method as claimed in claim 15, further comprising:
(e) applying a first underfill between the semiconductor element and the carrier; and
(f) applying a second underfill between the semiconductor element and the chips.